mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 08:05:26 +07:00
ab851d49f6
Pull x86 iopl updates from Ingo Molnar: "This implements a nice simplification of the iopl and ioperm code that Thomas Gleixner discovered: we can implement the IO privilege features of the iopl system call by using the IO permission bitmap in permissive mode, while trapping CLI/STI/POPF/PUSHF uses in user-space if they change the interrupt flag. This implements that feature, with testing facilities and related cleanups" [ "Simplification" may be an over-statement. The main goal is to avoid the cli/sti of iopl by effectively implementing the IO port access parts of iopl in terms of ioperm. This may end up not workign well in case people actually depend on cli/sti being available, or if there are mixed uses of iopl and ioperm. We will see.. - Linus ] * 'x86-iopl-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (22 commits) x86/ioperm: Fix use of deprecated config option x86/entry/32: Clarify register saving in __switch_to_asm() selftests/x86/iopl: Extend test to cover IOPL emulation x86/ioperm: Extend IOPL config to control ioperm() as well x86/iopl: Remove legacy IOPL option x86/iopl: Restrict iopl() permission scope x86/iopl: Fixup misleading comment selftests/x86/ioperm: Extend testing so the shared bitmap is exercised x86/ioperm: Share I/O bitmap if identical x86/ioperm: Remove bitmap if all permissions dropped x86/ioperm: Move TSS bitmap update to exit to user work x86/ioperm: Add bitmap sequence number x86/ioperm: Move iobitmap data into a struct x86/tss: Move I/O bitmap data into a seperate struct x86/io: Speedup schedule out of I/O bitmap user x86/ioperm: Avoid bitmap allocation if no permissions are set x86/ioperm: Simplify first ioperm() invocation logic x86/iopl: Cleanup include maze x86/tss: Fix and move VMX BUILD_BUG_ON() x86/cpu: Unify cpu_init() ...
1678 lines
42 KiB
ArmAsm
1678 lines
42 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 1991,1992 Linus Torvalds
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*
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* entry_32.S contains the system-call and low-level fault and trap handling routines.
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*
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* Stack layout while running C code:
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* ptrace needs to have all registers on the stack.
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* If the order here is changed, it needs to be
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* updated in fork.c:copy_process(), signal.c:do_signal(),
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* ptrace.c and ptrace.h
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*
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* 0(%esp) - %ebx
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* 4(%esp) - %ecx
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* 8(%esp) - %edx
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* C(%esp) - %esi
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* 10(%esp) - %edi
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* 14(%esp) - %ebp
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* 18(%esp) - %eax
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* 1C(%esp) - %ds
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* 20(%esp) - %es
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* 24(%esp) - %fs
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* 28(%esp) - %gs saved iff !CONFIG_X86_32_LAZY_GS
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* 2C(%esp) - orig_eax
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* 30(%esp) - %eip
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* 34(%esp) - %cs
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* 38(%esp) - %eflags
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* 3C(%esp) - %oldesp
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* 40(%esp) - %oldss
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*/
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#include <linux/linkage.h>
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#include <linux/err.h>
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#include <asm/thread_info.h>
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#include <asm/irqflags.h>
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#include <asm/errno.h>
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#include <asm/segment.h>
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#include <asm/smp.h>
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#include <asm/percpu.h>
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#include <asm/processor-flags.h>
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#include <asm/irq_vectors.h>
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#include <asm/cpufeatures.h>
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#include <asm/alternative-asm.h>
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#include <asm/asm.h>
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#include <asm/smap.h>
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#include <asm/frame.h>
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#include <asm/nospec-branch.h>
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#include "calling.h"
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.section .entry.text, "ax"
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/*
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* We use macros for low-level operations which need to be overridden
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* for paravirtualization. The following will never clobber any registers:
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* INTERRUPT_RETURN (aka. "iret")
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* GET_CR0_INTO_EAX (aka. "movl %cr0, %eax")
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* ENABLE_INTERRUPTS_SYSEXIT (aka "sti; sysexit").
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*
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* For DISABLE_INTERRUPTS/ENABLE_INTERRUPTS (aka "cli"/"sti"), you must
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* specify what registers can be overwritten (CLBR_NONE, CLBR_EAX/EDX/ECX/ANY).
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* Allowing a register to be clobbered can shrink the paravirt replacement
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* enough to patch inline, increasing performance.
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*/
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#ifdef CONFIG_PREEMPTION
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# define preempt_stop(clobbers) DISABLE_INTERRUPTS(clobbers); TRACE_IRQS_OFF
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#else
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# define preempt_stop(clobbers)
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#endif
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.macro TRACE_IRQS_IRET
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#ifdef CONFIG_TRACE_IRQFLAGS
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testl $X86_EFLAGS_IF, PT_EFLAGS(%esp) # interrupts off?
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jz 1f
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TRACE_IRQS_ON
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1:
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#endif
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.endm
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#define PTI_SWITCH_MASK (1 << PAGE_SHIFT)
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/*
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* User gs save/restore
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*
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* %gs is used for userland TLS and kernel only uses it for stack
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* canary which is required to be at %gs:20 by gcc. Read the comment
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* at the top of stackprotector.h for more info.
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*
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* Local labels 98 and 99 are used.
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*/
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#ifdef CONFIG_X86_32_LAZY_GS
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/* unfortunately push/pop can't be no-op */
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.macro PUSH_GS
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pushl $0
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.endm
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.macro POP_GS pop=0
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addl $(4 + \pop), %esp
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.endm
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.macro POP_GS_EX
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.endm
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/* all the rest are no-op */
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.macro PTGS_TO_GS
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.endm
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.macro PTGS_TO_GS_EX
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.endm
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.macro GS_TO_REG reg
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.endm
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.macro REG_TO_PTGS reg
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.endm
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.macro SET_KERNEL_GS reg
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.endm
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#else /* CONFIG_X86_32_LAZY_GS */
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.macro PUSH_GS
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pushl %gs
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.endm
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.macro POP_GS pop=0
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98: popl %gs
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.if \pop <> 0
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add $\pop, %esp
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.endif
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.endm
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.macro POP_GS_EX
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.pushsection .fixup, "ax"
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99: movl $0, (%esp)
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jmp 98b
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.popsection
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_ASM_EXTABLE(98b, 99b)
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.endm
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.macro PTGS_TO_GS
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98: mov PT_GS(%esp), %gs
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.endm
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.macro PTGS_TO_GS_EX
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.pushsection .fixup, "ax"
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99: movl $0, PT_GS(%esp)
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jmp 98b
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.popsection
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_ASM_EXTABLE(98b, 99b)
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.endm
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.macro GS_TO_REG reg
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movl %gs, \reg
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.endm
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.macro REG_TO_PTGS reg
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movl \reg, PT_GS(%esp)
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.endm
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.macro SET_KERNEL_GS reg
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movl $(__KERNEL_STACK_CANARY), \reg
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movl \reg, %gs
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.endm
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#endif /* CONFIG_X86_32_LAZY_GS */
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/* Unconditionally switch to user cr3 */
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.macro SWITCH_TO_USER_CR3 scratch_reg:req
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ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
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movl %cr3, \scratch_reg
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orl $PTI_SWITCH_MASK, \scratch_reg
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movl \scratch_reg, %cr3
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.Lend_\@:
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.endm
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.macro BUG_IF_WRONG_CR3 no_user_check=0
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#ifdef CONFIG_DEBUG_ENTRY
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ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
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.if \no_user_check == 0
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/* coming from usermode? */
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testl $USER_SEGMENT_RPL_MASK, PT_CS(%esp)
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jz .Lend_\@
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.endif
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/* On user-cr3? */
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movl %cr3, %eax
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testl $PTI_SWITCH_MASK, %eax
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jnz .Lend_\@
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/* From userspace with kernel cr3 - BUG */
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ud2
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.Lend_\@:
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#endif
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.endm
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/*
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* Switch to kernel cr3 if not already loaded and return current cr3 in
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* \scratch_reg
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*/
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.macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
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ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
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movl %cr3, \scratch_reg
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/* Test if we are already on kernel CR3 */
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testl $PTI_SWITCH_MASK, \scratch_reg
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jz .Lend_\@
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andl $(~PTI_SWITCH_MASK), \scratch_reg
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movl \scratch_reg, %cr3
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/* Return original CR3 in \scratch_reg */
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orl $PTI_SWITCH_MASK, \scratch_reg
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.Lend_\@:
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.endm
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#define CS_FROM_ENTRY_STACK (1 << 31)
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#define CS_FROM_USER_CR3 (1 << 30)
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#define CS_FROM_KERNEL (1 << 29)
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#define CS_FROM_ESPFIX (1 << 28)
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.macro FIXUP_FRAME
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/*
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* The high bits of the CS dword (__csh) are used for CS_FROM_*.
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* Clear them in case hardware didn't do this for us.
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*/
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andl $0x0000ffff, 4*4(%esp)
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#ifdef CONFIG_VM86
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testl $X86_EFLAGS_VM, 5*4(%esp)
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jnz .Lfrom_usermode_no_fixup_\@
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#endif
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testl $USER_SEGMENT_RPL_MASK, 4*4(%esp)
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jnz .Lfrom_usermode_no_fixup_\@
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orl $CS_FROM_KERNEL, 4*4(%esp)
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/*
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* When we're here from kernel mode; the (exception) stack looks like:
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*
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* 6*4(%esp) - <previous context>
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* 5*4(%esp) - flags
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* 4*4(%esp) - cs
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* 3*4(%esp) - ip
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* 2*4(%esp) - orig_eax
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* 1*4(%esp) - gs / function
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* 0*4(%esp) - fs
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*
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* Lets build a 5 entry IRET frame after that, such that struct pt_regs
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* is complete and in particular regs->sp is correct. This gives us
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* the original 6 enties as gap:
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*
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* 14*4(%esp) - <previous context>
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* 13*4(%esp) - gap / flags
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* 12*4(%esp) - gap / cs
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* 11*4(%esp) - gap / ip
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* 10*4(%esp) - gap / orig_eax
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* 9*4(%esp) - gap / gs / function
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* 8*4(%esp) - gap / fs
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* 7*4(%esp) - ss
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* 6*4(%esp) - sp
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* 5*4(%esp) - flags
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* 4*4(%esp) - cs
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* 3*4(%esp) - ip
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* 2*4(%esp) - orig_eax
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* 1*4(%esp) - gs / function
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* 0*4(%esp) - fs
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*/
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pushl %ss # ss
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pushl %esp # sp (points at ss)
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addl $7*4, (%esp) # point sp back at the previous context
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pushl 7*4(%esp) # flags
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pushl 7*4(%esp) # cs
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pushl 7*4(%esp) # ip
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pushl 7*4(%esp) # orig_eax
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pushl 7*4(%esp) # gs / function
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pushl 7*4(%esp) # fs
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.Lfrom_usermode_no_fixup_\@:
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.endm
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.macro IRET_FRAME
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/*
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* We're called with %ds, %es, %fs, and %gs from the interrupted
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* frame, so we shouldn't use them. Also, we may be in ESPFIX
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* mode and therefore have a nonzero SS base and an offset ESP,
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* so any attempt to access the stack needs to use SS. (except for
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* accesses through %esp, which automatically use SS.)
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*/
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testl $CS_FROM_KERNEL, 1*4(%esp)
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jz .Lfinished_frame_\@
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/*
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* Reconstruct the 3 entry IRET frame right after the (modified)
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* regs->sp without lowering %esp in between, such that an NMI in the
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* middle doesn't scribble our stack.
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*/
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pushl %eax
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pushl %ecx
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movl 5*4(%esp), %eax # (modified) regs->sp
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movl 4*4(%esp), %ecx # flags
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movl %ecx, %ss:-1*4(%eax)
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movl 3*4(%esp), %ecx # cs
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andl $0x0000ffff, %ecx
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movl %ecx, %ss:-2*4(%eax)
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movl 2*4(%esp), %ecx # ip
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movl %ecx, %ss:-3*4(%eax)
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movl 1*4(%esp), %ecx # eax
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movl %ecx, %ss:-4*4(%eax)
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popl %ecx
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lea -4*4(%eax), %esp
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popl %eax
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.Lfinished_frame_\@:
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.endm
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.macro SAVE_ALL pt_regs_ax=%eax switch_stacks=0 skip_gs=0 unwind_espfix=0
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cld
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.if \skip_gs == 0
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PUSH_GS
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.endif
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pushl %fs
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pushl %eax
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movl $(__KERNEL_PERCPU), %eax
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movl %eax, %fs
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.if \unwind_espfix > 0
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UNWIND_ESPFIX_STACK
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.endif
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popl %eax
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FIXUP_FRAME
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pushl %es
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pushl %ds
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pushl \pt_regs_ax
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pushl %ebp
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pushl %edi
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pushl %esi
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pushl %edx
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pushl %ecx
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pushl %ebx
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movl $(__USER_DS), %edx
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movl %edx, %ds
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movl %edx, %es
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.if \skip_gs == 0
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SET_KERNEL_GS %edx
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.endif
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/* Switch to kernel stack if necessary */
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.if \switch_stacks > 0
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SWITCH_TO_KERNEL_STACK
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.endif
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.endm
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.macro SAVE_ALL_NMI cr3_reg:req unwind_espfix=0
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SAVE_ALL unwind_espfix=\unwind_espfix
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BUG_IF_WRONG_CR3
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/*
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* Now switch the CR3 when PTI is enabled.
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*
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* We can enter with either user or kernel cr3, the code will
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* store the old cr3 in \cr3_reg and switches to the kernel cr3
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* if necessary.
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*/
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SWITCH_TO_KERNEL_CR3 scratch_reg=\cr3_reg
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.Lend_\@:
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.endm
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.macro RESTORE_INT_REGS
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popl %ebx
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popl %ecx
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popl %edx
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popl %esi
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popl %edi
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popl %ebp
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popl %eax
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.endm
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.macro RESTORE_REGS pop=0
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RESTORE_INT_REGS
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1: popl %ds
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2: popl %es
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3: popl %fs
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POP_GS \pop
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IRET_FRAME
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.pushsection .fixup, "ax"
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4: movl $0, (%esp)
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jmp 1b
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5: movl $0, (%esp)
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jmp 2b
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6: movl $0, (%esp)
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jmp 3b
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.popsection
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_ASM_EXTABLE(1b, 4b)
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_ASM_EXTABLE(2b, 5b)
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_ASM_EXTABLE(3b, 6b)
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POP_GS_EX
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.endm
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.macro RESTORE_ALL_NMI cr3_reg:req pop=0
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/*
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* Now switch the CR3 when PTI is enabled.
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*
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* We enter with kernel cr3 and switch the cr3 to the value
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* stored on \cr3_reg, which is either a user or a kernel cr3.
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*/
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ALTERNATIVE "jmp .Lswitched_\@", "", X86_FEATURE_PTI
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testl $PTI_SWITCH_MASK, \cr3_reg
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jz .Lswitched_\@
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/* User cr3 in \cr3_reg - write it to hardware cr3 */
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movl \cr3_reg, %cr3
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.Lswitched_\@:
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BUG_IF_WRONG_CR3
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RESTORE_REGS pop=\pop
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.endm
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.macro CHECK_AND_APPLY_ESPFIX
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#ifdef CONFIG_X86_ESPFIX32
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#define GDT_ESPFIX_OFFSET (GDT_ENTRY_ESPFIX_SS * 8)
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#define GDT_ESPFIX_SS PER_CPU_VAR(gdt_page) + GDT_ESPFIX_OFFSET
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ALTERNATIVE "jmp .Lend_\@", "", X86_BUG_ESPFIX
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movl PT_EFLAGS(%esp), %eax # mix EFLAGS, SS and CS
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/*
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* Warning: PT_OLDSS(%esp) contains the wrong/random values if we
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* are returning to the kernel.
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* See comments in process.c:copy_thread() for details.
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*/
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movb PT_OLDSS(%esp), %ah
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movb PT_CS(%esp), %al
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andl $(X86_EFLAGS_VM | (SEGMENT_TI_MASK << 8) | SEGMENT_RPL_MASK), %eax
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cmpl $((SEGMENT_LDT << 8) | USER_RPL), %eax
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jne .Lend_\@ # returning to user-space with LDT SS
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/*
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* Setup and switch to ESPFIX stack
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*
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* We're returning to userspace with a 16 bit stack. The CPU will not
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* restore the high word of ESP for us on executing iret... This is an
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* "official" bug of all the x86-compatible CPUs, which we can work
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* around to make dosemu and wine happy. We do this by preloading the
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* high word of ESP with the high word of the userspace ESP while
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* compensating for the offset by changing to the ESPFIX segment with
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* a base address that matches for the difference.
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*/
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mov %esp, %edx /* load kernel esp */
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mov PT_OLDESP(%esp), %eax /* load userspace esp */
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mov %dx, %ax /* eax: new kernel esp */
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sub %eax, %edx /* offset (low word is 0) */
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shr $16, %edx
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mov %dl, GDT_ESPFIX_SS + 4 /* bits 16..23 */
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mov %dh, GDT_ESPFIX_SS + 7 /* bits 24..31 */
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pushl $__ESPFIX_SS
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pushl %eax /* new kernel esp */
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/*
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* Disable interrupts, but do not irqtrace this section: we
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* will soon execute iret and the tracer was already set to
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* the irqstate after the IRET:
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*/
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DISABLE_INTERRUPTS(CLBR_ANY)
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lss (%esp), %esp /* switch to espfix segment */
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.Lend_\@:
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#endif /* CONFIG_X86_ESPFIX32 */
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.endm
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/*
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* Called with pt_regs fully populated and kernel segments loaded,
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* so we can access PER_CPU and use the integer registers.
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*
|
|
* We need to be very careful here with the %esp switch, because an NMI
|
|
* can happen everywhere. If the NMI handler finds itself on the
|
|
* entry-stack, it will overwrite the task-stack and everything we
|
|
* copied there. So allocate the stack-frame on the task-stack and
|
|
* switch to it before we do any copying.
|
|
*/
|
|
|
|
.macro SWITCH_TO_KERNEL_STACK
|
|
|
|
ALTERNATIVE "", "jmp .Lend_\@", X86_FEATURE_XENPV
|
|
|
|
BUG_IF_WRONG_CR3
|
|
|
|
SWITCH_TO_KERNEL_CR3 scratch_reg=%eax
|
|
|
|
/*
|
|
* %eax now contains the entry cr3 and we carry it forward in
|
|
* that register for the time this macro runs
|
|
*/
|
|
|
|
/* Are we on the entry stack? Bail out if not! */
|
|
movl PER_CPU_VAR(cpu_entry_area), %ecx
|
|
addl $CPU_ENTRY_AREA_entry_stack + SIZEOF_entry_stack, %ecx
|
|
subl %esp, %ecx /* ecx = (end of entry_stack) - esp */
|
|
cmpl $SIZEOF_entry_stack, %ecx
|
|
jae .Lend_\@
|
|
|
|
/* Load stack pointer into %esi and %edi */
|
|
movl %esp, %esi
|
|
movl %esi, %edi
|
|
|
|
/* Move %edi to the top of the entry stack */
|
|
andl $(MASK_entry_stack), %edi
|
|
addl $(SIZEOF_entry_stack), %edi
|
|
|
|
/* Load top of task-stack into %edi */
|
|
movl TSS_entry2task_stack(%edi), %edi
|
|
|
|
/* Special case - entry from kernel mode via entry stack */
|
|
#ifdef CONFIG_VM86
|
|
movl PT_EFLAGS(%esp), %ecx # mix EFLAGS and CS
|
|
movb PT_CS(%esp), %cl
|
|
andl $(X86_EFLAGS_VM | SEGMENT_RPL_MASK), %ecx
|
|
#else
|
|
movl PT_CS(%esp), %ecx
|
|
andl $SEGMENT_RPL_MASK, %ecx
|
|
#endif
|
|
cmpl $USER_RPL, %ecx
|
|
jb .Lentry_from_kernel_\@
|
|
|
|
/* Bytes to copy */
|
|
movl $PTREGS_SIZE, %ecx
|
|
|
|
#ifdef CONFIG_VM86
|
|
testl $X86_EFLAGS_VM, PT_EFLAGS(%esi)
|
|
jz .Lcopy_pt_regs_\@
|
|
|
|
/*
|
|
* Stack-frame contains 4 additional segment registers when
|
|
* coming from VM86 mode
|
|
*/
|
|
addl $(4 * 4), %ecx
|
|
|
|
#endif
|
|
.Lcopy_pt_regs_\@:
|
|
|
|
/* Allocate frame on task-stack */
|
|
subl %ecx, %edi
|
|
|
|
/* Switch to task-stack */
|
|
movl %edi, %esp
|
|
|
|
/*
|
|
* We are now on the task-stack and can safely copy over the
|
|
* stack-frame
|
|
*/
|
|
shrl $2, %ecx
|
|
cld
|
|
rep movsl
|
|
|
|
jmp .Lend_\@
|
|
|
|
.Lentry_from_kernel_\@:
|
|
|
|
/*
|
|
* This handles the case when we enter the kernel from
|
|
* kernel-mode and %esp points to the entry-stack. When this
|
|
* happens we need to switch to the task-stack to run C code,
|
|
* but switch back to the entry-stack again when we approach
|
|
* iret and return to the interrupted code-path. This usually
|
|
* happens when we hit an exception while restoring user-space
|
|
* segment registers on the way back to user-space or when the
|
|
* sysenter handler runs with eflags.tf set.
|
|
*
|
|
* When we switch to the task-stack here, we can't trust the
|
|
* contents of the entry-stack anymore, as the exception handler
|
|
* might be scheduled out or moved to another CPU. Therefore we
|
|
* copy the complete entry-stack to the task-stack and set a
|
|
* marker in the iret-frame (bit 31 of the CS dword) to detect
|
|
* what we've done on the iret path.
|
|
*
|
|
* On the iret path we copy everything back and switch to the
|
|
* entry-stack, so that the interrupted kernel code-path
|
|
* continues on the same stack it was interrupted with.
|
|
*
|
|
* Be aware that an NMI can happen anytime in this code.
|
|
*
|
|
* %esi: Entry-Stack pointer (same as %esp)
|
|
* %edi: Top of the task stack
|
|
* %eax: CR3 on kernel entry
|
|
*/
|
|
|
|
/* Calculate number of bytes on the entry stack in %ecx */
|
|
movl %esi, %ecx
|
|
|
|
/* %ecx to the top of entry-stack */
|
|
andl $(MASK_entry_stack), %ecx
|
|
addl $(SIZEOF_entry_stack), %ecx
|
|
|
|
/* Number of bytes on the entry stack to %ecx */
|
|
sub %esi, %ecx
|
|
|
|
/* Mark stackframe as coming from entry stack */
|
|
orl $CS_FROM_ENTRY_STACK, PT_CS(%esp)
|
|
|
|
/*
|
|
* Test the cr3 used to enter the kernel and add a marker
|
|
* so that we can switch back to it before iret.
|
|
*/
|
|
testl $PTI_SWITCH_MASK, %eax
|
|
jz .Lcopy_pt_regs_\@
|
|
orl $CS_FROM_USER_CR3, PT_CS(%esp)
|
|
|
|
/*
|
|
* %esi and %edi are unchanged, %ecx contains the number of
|
|
* bytes to copy. The code at .Lcopy_pt_regs_\@ will allocate
|
|
* the stack-frame on task-stack and copy everything over
|
|
*/
|
|
jmp .Lcopy_pt_regs_\@
|
|
|
|
.Lend_\@:
|
|
.endm
|
|
|
|
/*
|
|
* Switch back from the kernel stack to the entry stack.
|
|
*
|
|
* The %esp register must point to pt_regs on the task stack. It will
|
|
* first calculate the size of the stack-frame to copy, depending on
|
|
* whether we return to VM86 mode or not. With that it uses 'rep movsl'
|
|
* to copy the contents of the stack over to the entry stack.
|
|
*
|
|
* We must be very careful here, as we can't trust the contents of the
|
|
* task-stack once we switched to the entry-stack. When an NMI happens
|
|
* while on the entry-stack, the NMI handler will switch back to the top
|
|
* of the task stack, overwriting our stack-frame we are about to copy.
|
|
* Therefore we switch the stack only after everything is copied over.
|
|
*/
|
|
.macro SWITCH_TO_ENTRY_STACK
|
|
|
|
ALTERNATIVE "", "jmp .Lend_\@", X86_FEATURE_XENPV
|
|
|
|
/* Bytes to copy */
|
|
movl $PTREGS_SIZE, %ecx
|
|
|
|
#ifdef CONFIG_VM86
|
|
testl $(X86_EFLAGS_VM), PT_EFLAGS(%esp)
|
|
jz .Lcopy_pt_regs_\@
|
|
|
|
/* Additional 4 registers to copy when returning to VM86 mode */
|
|
addl $(4 * 4), %ecx
|
|
|
|
.Lcopy_pt_regs_\@:
|
|
#endif
|
|
|
|
/* Initialize source and destination for movsl */
|
|
movl PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %edi
|
|
subl %ecx, %edi
|
|
movl %esp, %esi
|
|
|
|
/* Save future stack pointer in %ebx */
|
|
movl %edi, %ebx
|
|
|
|
/* Copy over the stack-frame */
|
|
shrl $2, %ecx
|
|
cld
|
|
rep movsl
|
|
|
|
/*
|
|
* Switch to entry-stack - needs to happen after everything is
|
|
* copied because the NMI handler will overwrite the task-stack
|
|
* when on entry-stack
|
|
*/
|
|
movl %ebx, %esp
|
|
|
|
.Lend_\@:
|
|
.endm
|
|
|
|
/*
|
|
* This macro handles the case when we return to kernel-mode on the iret
|
|
* path and have to switch back to the entry stack and/or user-cr3
|
|
*
|
|
* See the comments below the .Lentry_from_kernel_\@ label in the
|
|
* SWITCH_TO_KERNEL_STACK macro for more details.
|
|
*/
|
|
.macro PARANOID_EXIT_TO_KERNEL_MODE
|
|
|
|
/*
|
|
* Test if we entered the kernel with the entry-stack. Most
|
|
* likely we did not, because this code only runs on the
|
|
* return-to-kernel path.
|
|
*/
|
|
testl $CS_FROM_ENTRY_STACK, PT_CS(%esp)
|
|
jz .Lend_\@
|
|
|
|
/* Unlikely slow-path */
|
|
|
|
/* Clear marker from stack-frame */
|
|
andl $(~CS_FROM_ENTRY_STACK), PT_CS(%esp)
|
|
|
|
/* Copy the remaining task-stack contents to entry-stack */
|
|
movl %esp, %esi
|
|
movl PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %edi
|
|
|
|
/* Bytes on the task-stack to ecx */
|
|
movl PER_CPU_VAR(cpu_tss_rw + TSS_sp1), %ecx
|
|
subl %esi, %ecx
|
|
|
|
/* Allocate stack-frame on entry-stack */
|
|
subl %ecx, %edi
|
|
|
|
/*
|
|
* Save future stack-pointer, we must not switch until the
|
|
* copy is done, otherwise the NMI handler could destroy the
|
|
* contents of the task-stack we are about to copy.
|
|
*/
|
|
movl %edi, %ebx
|
|
|
|
/* Do the copy */
|
|
shrl $2, %ecx
|
|
cld
|
|
rep movsl
|
|
|
|
/* Safe to switch to entry-stack now */
|
|
movl %ebx, %esp
|
|
|
|
/*
|
|
* We came from entry-stack and need to check if we also need to
|
|
* switch back to user cr3.
|
|
*/
|
|
testl $CS_FROM_USER_CR3, PT_CS(%esp)
|
|
jz .Lend_\@
|
|
|
|
/* Clear marker from stack-frame */
|
|
andl $(~CS_FROM_USER_CR3), PT_CS(%esp)
|
|
|
|
SWITCH_TO_USER_CR3 scratch_reg=%eax
|
|
|
|
.Lend_\@:
|
|
.endm
|
|
/*
|
|
* %eax: prev task
|
|
* %edx: next task
|
|
*/
|
|
SYM_CODE_START(__switch_to_asm)
|
|
/*
|
|
* Save callee-saved registers
|
|
* This must match the order in struct inactive_task_frame
|
|
*/
|
|
pushl %ebp
|
|
pushl %ebx
|
|
pushl %edi
|
|
pushl %esi
|
|
/*
|
|
* Flags are saved to prevent AC leakage. This could go
|
|
* away if objtool would have 32bit support to verify
|
|
* the STAC/CLAC correctness.
|
|
*/
|
|
pushfl
|
|
|
|
/* switch stack */
|
|
movl %esp, TASK_threadsp(%eax)
|
|
movl TASK_threadsp(%edx), %esp
|
|
|
|
#ifdef CONFIG_STACKPROTECTOR
|
|
movl TASK_stack_canary(%edx), %ebx
|
|
movl %ebx, PER_CPU_VAR(stack_canary)+stack_canary_offset
|
|
#endif
|
|
|
|
#ifdef CONFIG_RETPOLINE
|
|
/*
|
|
* When switching from a shallower to a deeper call stack
|
|
* the RSB may either underflow or use entries populated
|
|
* with userspace addresses. On CPUs where those concerns
|
|
* exist, overwrite the RSB with entries which capture
|
|
* speculative execution to prevent attack.
|
|
*/
|
|
FILL_RETURN_BUFFER %ebx, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
|
|
#endif
|
|
|
|
/* Restore flags or the incoming task to restore AC state. */
|
|
popfl
|
|
/* restore callee-saved registers */
|
|
popl %esi
|
|
popl %edi
|
|
popl %ebx
|
|
popl %ebp
|
|
|
|
jmp __switch_to
|
|
SYM_CODE_END(__switch_to_asm)
|
|
|
|
/*
|
|
* The unwinder expects the last frame on the stack to always be at the same
|
|
* offset from the end of the page, which allows it to validate the stack.
|
|
* Calling schedule_tail() directly would break that convention because its an
|
|
* asmlinkage function so its argument has to be pushed on the stack. This
|
|
* wrapper creates a proper "end of stack" frame header before the call.
|
|
*/
|
|
SYM_FUNC_START(schedule_tail_wrapper)
|
|
FRAME_BEGIN
|
|
|
|
pushl %eax
|
|
call schedule_tail
|
|
popl %eax
|
|
|
|
FRAME_END
|
|
ret
|
|
SYM_FUNC_END(schedule_tail_wrapper)
|
|
/*
|
|
* A newly forked process directly context switches into this address.
|
|
*
|
|
* eax: prev task we switched from
|
|
* ebx: kernel thread func (NULL for user thread)
|
|
* edi: kernel thread arg
|
|
*/
|
|
SYM_CODE_START(ret_from_fork)
|
|
call schedule_tail_wrapper
|
|
|
|
testl %ebx, %ebx
|
|
jnz 1f /* kernel threads are uncommon */
|
|
|
|
2:
|
|
/* When we fork, we trace the syscall return in the child, too. */
|
|
movl %esp, %eax
|
|
call syscall_return_slowpath
|
|
STACKLEAK_ERASE
|
|
jmp restore_all
|
|
|
|
/* kernel thread */
|
|
1: movl %edi, %eax
|
|
CALL_NOSPEC %ebx
|
|
/*
|
|
* A kernel thread is allowed to return here after successfully
|
|
* calling do_execve(). Exit to userspace to complete the execve()
|
|
* syscall.
|
|
*/
|
|
movl $0, PT_EAX(%esp)
|
|
jmp 2b
|
|
SYM_CODE_END(ret_from_fork)
|
|
|
|
/*
|
|
* Return to user mode is not as complex as all this looks,
|
|
* but we want the default path for a system call return to
|
|
* go as quickly as possible which is why some of this is
|
|
* less clear than it otherwise should be.
|
|
*/
|
|
|
|
# userspace resumption stub bypassing syscall exit tracing
|
|
SYM_CODE_START_LOCAL(ret_from_exception)
|
|
preempt_stop(CLBR_ANY)
|
|
ret_from_intr:
|
|
#ifdef CONFIG_VM86
|
|
movl PT_EFLAGS(%esp), %eax # mix EFLAGS and CS
|
|
movb PT_CS(%esp), %al
|
|
andl $(X86_EFLAGS_VM | SEGMENT_RPL_MASK), %eax
|
|
#else
|
|
/*
|
|
* We can be coming here from child spawned by kernel_thread().
|
|
*/
|
|
movl PT_CS(%esp), %eax
|
|
andl $SEGMENT_RPL_MASK, %eax
|
|
#endif
|
|
cmpl $USER_RPL, %eax
|
|
jb restore_all_kernel # not returning to v8086 or userspace
|
|
|
|
DISABLE_INTERRUPTS(CLBR_ANY)
|
|
TRACE_IRQS_OFF
|
|
movl %esp, %eax
|
|
call prepare_exit_to_usermode
|
|
jmp restore_all
|
|
SYM_CODE_END(ret_from_exception)
|
|
|
|
SYM_ENTRY(__begin_SYSENTER_singlestep_region, SYM_L_GLOBAL, SYM_A_NONE)
|
|
/*
|
|
* All code from here through __end_SYSENTER_singlestep_region is subject
|
|
* to being single-stepped if a user program sets TF and executes SYSENTER.
|
|
* There is absolutely nothing that we can do to prevent this from happening
|
|
* (thanks Intel!). To keep our handling of this situation as simple as
|
|
* possible, we handle TF just like AC and NT, except that our #DB handler
|
|
* will ignore all of the single-step traps generated in this range.
|
|
*/
|
|
|
|
#ifdef CONFIG_XEN_PV
|
|
/*
|
|
* Xen doesn't set %esp to be precisely what the normal SYSENTER
|
|
* entry point expects, so fix it up before using the normal path.
|
|
*/
|
|
SYM_CODE_START(xen_sysenter_target)
|
|
addl $5*4, %esp /* remove xen-provided frame */
|
|
jmp .Lsysenter_past_esp
|
|
SYM_CODE_END(xen_sysenter_target)
|
|
#endif
|
|
|
|
/*
|
|
* 32-bit SYSENTER entry.
|
|
*
|
|
* 32-bit system calls through the vDSO's __kernel_vsyscall enter here
|
|
* if X86_FEATURE_SEP is available. This is the preferred system call
|
|
* entry on 32-bit systems.
|
|
*
|
|
* The SYSENTER instruction, in principle, should *only* occur in the
|
|
* vDSO. In practice, a small number of Android devices were shipped
|
|
* with a copy of Bionic that inlined a SYSENTER instruction. This
|
|
* never happened in any of Google's Bionic versions -- it only happened
|
|
* in a narrow range of Intel-provided versions.
|
|
*
|
|
* SYSENTER loads SS, ESP, CS, and EIP from previously programmed MSRs.
|
|
* IF and VM in RFLAGS are cleared (IOW: interrupts are off).
|
|
* SYSENTER does not save anything on the stack,
|
|
* and does not save old EIP (!!!), ESP, or EFLAGS.
|
|
*
|
|
* To avoid losing track of EFLAGS.VM (and thus potentially corrupting
|
|
* user and/or vm86 state), we explicitly disable the SYSENTER
|
|
* instruction in vm86 mode by reprogramming the MSRs.
|
|
*
|
|
* Arguments:
|
|
* eax system call number
|
|
* ebx arg1
|
|
* ecx arg2
|
|
* edx arg3
|
|
* esi arg4
|
|
* edi arg5
|
|
* ebp user stack
|
|
* 0(%ebp) arg6
|
|
*/
|
|
SYM_FUNC_START(entry_SYSENTER_32)
|
|
/*
|
|
* On entry-stack with all userspace-regs live - save and
|
|
* restore eflags and %eax to use it as scratch-reg for the cr3
|
|
* switch.
|
|
*/
|
|
pushfl
|
|
pushl %eax
|
|
BUG_IF_WRONG_CR3 no_user_check=1
|
|
SWITCH_TO_KERNEL_CR3 scratch_reg=%eax
|
|
popl %eax
|
|
popfl
|
|
|
|
/* Stack empty again, switch to task stack */
|
|
movl TSS_entry2task_stack(%esp), %esp
|
|
|
|
.Lsysenter_past_esp:
|
|
pushl $__USER_DS /* pt_regs->ss */
|
|
pushl %ebp /* pt_regs->sp (stashed in bp) */
|
|
pushfl /* pt_regs->flags (except IF = 0) */
|
|
orl $X86_EFLAGS_IF, (%esp) /* Fix IF */
|
|
pushl $__USER_CS /* pt_regs->cs */
|
|
pushl $0 /* pt_regs->ip = 0 (placeholder) */
|
|
pushl %eax /* pt_regs->orig_ax */
|
|
SAVE_ALL pt_regs_ax=$-ENOSYS /* save rest, stack already switched */
|
|
|
|
/*
|
|
* SYSENTER doesn't filter flags, so we need to clear NT, AC
|
|
* and TF ourselves. To save a few cycles, we can check whether
|
|
* either was set instead of doing an unconditional popfq.
|
|
* This needs to happen before enabling interrupts so that
|
|
* we don't get preempted with NT set.
|
|
*
|
|
* If TF is set, we will single-step all the way to here -- do_debug
|
|
* will ignore all the traps. (Yes, this is slow, but so is
|
|
* single-stepping in general. This allows us to avoid having
|
|
* a more complicated code to handle the case where a user program
|
|
* forces us to single-step through the SYSENTER entry code.)
|
|
*
|
|
* NB.: .Lsysenter_fix_flags is a label with the code under it moved
|
|
* out-of-line as an optimization: NT is unlikely to be set in the
|
|
* majority of the cases and instead of polluting the I$ unnecessarily,
|
|
* we're keeping that code behind a branch which will predict as
|
|
* not-taken and therefore its instructions won't be fetched.
|
|
*/
|
|
testl $X86_EFLAGS_NT|X86_EFLAGS_AC|X86_EFLAGS_TF, PT_EFLAGS(%esp)
|
|
jnz .Lsysenter_fix_flags
|
|
.Lsysenter_flags_fixed:
|
|
|
|
/*
|
|
* User mode is traced as though IRQs are on, and SYSENTER
|
|
* turned them off.
|
|
*/
|
|
TRACE_IRQS_OFF
|
|
|
|
movl %esp, %eax
|
|
call do_fast_syscall_32
|
|
/* XEN PV guests always use IRET path */
|
|
ALTERNATIVE "testl %eax, %eax; jz .Lsyscall_32_done", \
|
|
"jmp .Lsyscall_32_done", X86_FEATURE_XENPV
|
|
|
|
STACKLEAK_ERASE
|
|
|
|
/* Opportunistic SYSEXIT */
|
|
TRACE_IRQS_ON /* User mode traces as IRQs on. */
|
|
|
|
/*
|
|
* Setup entry stack - we keep the pointer in %eax and do the
|
|
* switch after almost all user-state is restored.
|
|
*/
|
|
|
|
/* Load entry stack pointer and allocate frame for eflags/eax */
|
|
movl PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %eax
|
|
subl $(2*4), %eax
|
|
|
|
/* Copy eflags and eax to entry stack */
|
|
movl PT_EFLAGS(%esp), %edi
|
|
movl PT_EAX(%esp), %esi
|
|
movl %edi, (%eax)
|
|
movl %esi, 4(%eax)
|
|
|
|
/* Restore user registers and segments */
|
|
movl PT_EIP(%esp), %edx /* pt_regs->ip */
|
|
movl PT_OLDESP(%esp), %ecx /* pt_regs->sp */
|
|
1: mov PT_FS(%esp), %fs
|
|
PTGS_TO_GS
|
|
|
|
popl %ebx /* pt_regs->bx */
|
|
addl $2*4, %esp /* skip pt_regs->cx and pt_regs->dx */
|
|
popl %esi /* pt_regs->si */
|
|
popl %edi /* pt_regs->di */
|
|
popl %ebp /* pt_regs->bp */
|
|
|
|
/* Switch to entry stack */
|
|
movl %eax, %esp
|
|
|
|
/* Now ready to switch the cr3 */
|
|
SWITCH_TO_USER_CR3 scratch_reg=%eax
|
|
|
|
/*
|
|
* Restore all flags except IF. (We restore IF separately because
|
|
* STI gives a one-instruction window in which we won't be interrupted,
|
|
* whereas POPF does not.)
|
|
*/
|
|
btrl $X86_EFLAGS_IF_BIT, (%esp)
|
|
BUG_IF_WRONG_CR3 no_user_check=1
|
|
popfl
|
|
popl %eax
|
|
|
|
/*
|
|
* Return back to the vDSO, which will pop ecx and edx.
|
|
* Don't bother with DS and ES (they already contain __USER_DS).
|
|
*/
|
|
sti
|
|
sysexit
|
|
|
|
.pushsection .fixup, "ax"
|
|
2: movl $0, PT_FS(%esp)
|
|
jmp 1b
|
|
.popsection
|
|
_ASM_EXTABLE(1b, 2b)
|
|
PTGS_TO_GS_EX
|
|
|
|
.Lsysenter_fix_flags:
|
|
pushl $X86_EFLAGS_FIXED
|
|
popfl
|
|
jmp .Lsysenter_flags_fixed
|
|
SYM_ENTRY(__end_SYSENTER_singlestep_region, SYM_L_GLOBAL, SYM_A_NONE)
|
|
SYM_FUNC_END(entry_SYSENTER_32)
|
|
|
|
/*
|
|
* 32-bit legacy system call entry.
|
|
*
|
|
* 32-bit x86 Linux system calls traditionally used the INT $0x80
|
|
* instruction. INT $0x80 lands here.
|
|
*
|
|
* This entry point can be used by any 32-bit perform system calls.
|
|
* Instances of INT $0x80 can be found inline in various programs and
|
|
* libraries. It is also used by the vDSO's __kernel_vsyscall
|
|
* fallback for hardware that doesn't support a faster entry method.
|
|
* Restarted 32-bit system calls also fall back to INT $0x80
|
|
* regardless of what instruction was originally used to do the system
|
|
* call. (64-bit programs can use INT $0x80 as well, but they can
|
|
* only run on 64-bit kernels and therefore land in
|
|
* entry_INT80_compat.)
|
|
*
|
|
* This is considered a slow path. It is not used by most libc
|
|
* implementations on modern hardware except during process startup.
|
|
*
|
|
* Arguments:
|
|
* eax system call number
|
|
* ebx arg1
|
|
* ecx arg2
|
|
* edx arg3
|
|
* esi arg4
|
|
* edi arg5
|
|
* ebp arg6
|
|
*/
|
|
SYM_FUNC_START(entry_INT80_32)
|
|
ASM_CLAC
|
|
pushl %eax /* pt_regs->orig_ax */
|
|
|
|
SAVE_ALL pt_regs_ax=$-ENOSYS switch_stacks=1 /* save rest */
|
|
|
|
/*
|
|
* User mode is traced as though IRQs are on, and the interrupt gate
|
|
* turned them off.
|
|
*/
|
|
TRACE_IRQS_OFF
|
|
|
|
movl %esp, %eax
|
|
call do_int80_syscall_32
|
|
.Lsyscall_32_done:
|
|
|
|
STACKLEAK_ERASE
|
|
|
|
restore_all:
|
|
TRACE_IRQS_IRET
|
|
SWITCH_TO_ENTRY_STACK
|
|
.Lrestore_all_notrace:
|
|
CHECK_AND_APPLY_ESPFIX
|
|
.Lrestore_nocheck:
|
|
/* Switch back to user CR3 */
|
|
SWITCH_TO_USER_CR3 scratch_reg=%eax
|
|
|
|
BUG_IF_WRONG_CR3
|
|
|
|
/* Restore user state */
|
|
RESTORE_REGS pop=4 # skip orig_eax/error_code
|
|
.Lirq_return:
|
|
/*
|
|
* ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization
|
|
* when returning from IPI handler and when returning from
|
|
* scheduler to user-space.
|
|
*/
|
|
INTERRUPT_RETURN
|
|
|
|
restore_all_kernel:
|
|
#ifdef CONFIG_PREEMPTION
|
|
DISABLE_INTERRUPTS(CLBR_ANY)
|
|
cmpl $0, PER_CPU_VAR(__preempt_count)
|
|
jnz .Lno_preempt
|
|
testl $X86_EFLAGS_IF, PT_EFLAGS(%esp) # interrupts off (exception path) ?
|
|
jz .Lno_preempt
|
|
call preempt_schedule_irq
|
|
.Lno_preempt:
|
|
#endif
|
|
TRACE_IRQS_IRET
|
|
PARANOID_EXIT_TO_KERNEL_MODE
|
|
BUG_IF_WRONG_CR3
|
|
RESTORE_REGS 4
|
|
jmp .Lirq_return
|
|
|
|
.section .fixup, "ax"
|
|
SYM_CODE_START(iret_exc)
|
|
pushl $0 # no error code
|
|
pushl $do_iret_error
|
|
|
|
#ifdef CONFIG_DEBUG_ENTRY
|
|
/*
|
|
* The stack-frame here is the one that iret faulted on, so its a
|
|
* return-to-user frame. We are on kernel-cr3 because we come here from
|
|
* the fixup code. This confuses the CR3 checker, so switch to user-cr3
|
|
* as the checker expects it.
|
|
*/
|
|
pushl %eax
|
|
SWITCH_TO_USER_CR3 scratch_reg=%eax
|
|
popl %eax
|
|
#endif
|
|
|
|
jmp common_exception
|
|
SYM_CODE_END(iret_exc)
|
|
.previous
|
|
_ASM_EXTABLE(.Lirq_return, iret_exc)
|
|
SYM_FUNC_END(entry_INT80_32)
|
|
|
|
.macro FIXUP_ESPFIX_STACK
|
|
/*
|
|
* Switch back for ESPFIX stack to the normal zerobased stack
|
|
*
|
|
* We can't call C functions using the ESPFIX stack. This code reads
|
|
* the high word of the segment base from the GDT and swiches to the
|
|
* normal stack and adjusts ESP with the matching offset.
|
|
*
|
|
* We might be on user CR3 here, so percpu data is not mapped and we can't
|
|
* access the GDT through the percpu segment. Instead, use SGDT to find
|
|
* the cpu_entry_area alias of the GDT.
|
|
*/
|
|
#ifdef CONFIG_X86_ESPFIX32
|
|
/* fixup the stack */
|
|
pushl %ecx
|
|
subl $2*4, %esp
|
|
sgdt (%esp)
|
|
movl 2(%esp), %ecx /* GDT address */
|
|
/*
|
|
* Careful: ECX is a linear pointer, so we need to force base
|
|
* zero. %cs is the only known-linear segment we have right now.
|
|
*/
|
|
mov %cs:GDT_ESPFIX_OFFSET + 4(%ecx), %al /* bits 16..23 */
|
|
mov %cs:GDT_ESPFIX_OFFSET + 7(%ecx), %ah /* bits 24..31 */
|
|
shl $16, %eax
|
|
addl $2*4, %esp
|
|
popl %ecx
|
|
addl %esp, %eax /* the adjusted stack pointer */
|
|
pushl $__KERNEL_DS
|
|
pushl %eax
|
|
lss (%esp), %esp /* switch to the normal stack segment */
|
|
#endif
|
|
.endm
|
|
|
|
.macro UNWIND_ESPFIX_STACK
|
|
/* It's safe to clobber %eax, all other regs need to be preserved */
|
|
#ifdef CONFIG_X86_ESPFIX32
|
|
movl %ss, %eax
|
|
/* see if on espfix stack */
|
|
cmpw $__ESPFIX_SS, %ax
|
|
jne .Lno_fixup_\@
|
|
/* switch to normal stack */
|
|
FIXUP_ESPFIX_STACK
|
|
.Lno_fixup_\@:
|
|
#endif
|
|
.endm
|
|
|
|
/*
|
|
* Build the entry stubs with some assembler magic.
|
|
* We pack 1 stub into every 8-byte block.
|
|
*/
|
|
.align 8
|
|
SYM_CODE_START(irq_entries_start)
|
|
vector=FIRST_EXTERNAL_VECTOR
|
|
.rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR)
|
|
pushl $(~vector+0x80) /* Note: always in signed byte range */
|
|
vector=vector+1
|
|
jmp common_interrupt
|
|
.align 8
|
|
.endr
|
|
SYM_CODE_END(irq_entries_start)
|
|
|
|
#ifdef CONFIG_X86_LOCAL_APIC
|
|
.align 8
|
|
SYM_CODE_START(spurious_entries_start)
|
|
vector=FIRST_SYSTEM_VECTOR
|
|
.rept (NR_VECTORS - FIRST_SYSTEM_VECTOR)
|
|
pushl $(~vector+0x80) /* Note: always in signed byte range */
|
|
vector=vector+1
|
|
jmp common_spurious
|
|
.align 8
|
|
.endr
|
|
SYM_CODE_END(spurious_entries_start)
|
|
|
|
SYM_CODE_START_LOCAL(common_spurious)
|
|
ASM_CLAC
|
|
addl $-0x80, (%esp) /* Adjust vector into the [-256, -1] range */
|
|
SAVE_ALL switch_stacks=1
|
|
ENCODE_FRAME_POINTER
|
|
TRACE_IRQS_OFF
|
|
movl %esp, %eax
|
|
call smp_spurious_interrupt
|
|
jmp ret_from_intr
|
|
SYM_CODE_END(common_spurious)
|
|
#endif
|
|
|
|
/*
|
|
* the CPU automatically disables interrupts when executing an IRQ vector,
|
|
* so IRQ-flags tracing has to follow that:
|
|
*/
|
|
.p2align CONFIG_X86_L1_CACHE_SHIFT
|
|
SYM_CODE_START_LOCAL(common_interrupt)
|
|
ASM_CLAC
|
|
addl $-0x80, (%esp) /* Adjust vector into the [-256, -1] range */
|
|
|
|
SAVE_ALL switch_stacks=1
|
|
ENCODE_FRAME_POINTER
|
|
TRACE_IRQS_OFF
|
|
movl %esp, %eax
|
|
call do_IRQ
|
|
jmp ret_from_intr
|
|
SYM_CODE_END(common_interrupt)
|
|
|
|
#define BUILD_INTERRUPT3(name, nr, fn) \
|
|
SYM_FUNC_START(name) \
|
|
ASM_CLAC; \
|
|
pushl $~(nr); \
|
|
SAVE_ALL switch_stacks=1; \
|
|
ENCODE_FRAME_POINTER; \
|
|
TRACE_IRQS_OFF \
|
|
movl %esp, %eax; \
|
|
call fn; \
|
|
jmp ret_from_intr; \
|
|
SYM_FUNC_END(name)
|
|
|
|
#define BUILD_INTERRUPT(name, nr) \
|
|
BUILD_INTERRUPT3(name, nr, smp_##name); \
|
|
|
|
/* The include is where all of the SMP etc. interrupts come from */
|
|
#include <asm/entry_arch.h>
|
|
|
|
SYM_CODE_START(coprocessor_error)
|
|
ASM_CLAC
|
|
pushl $0
|
|
pushl $do_coprocessor_error
|
|
jmp common_exception
|
|
SYM_CODE_END(coprocessor_error)
|
|
|
|
SYM_CODE_START(simd_coprocessor_error)
|
|
ASM_CLAC
|
|
pushl $0
|
|
#ifdef CONFIG_X86_INVD_BUG
|
|
/* AMD 486 bug: invd from userspace calls exception 19 instead of #GP */
|
|
ALTERNATIVE "pushl $do_general_protection", \
|
|
"pushl $do_simd_coprocessor_error", \
|
|
X86_FEATURE_XMM
|
|
#else
|
|
pushl $do_simd_coprocessor_error
|
|
#endif
|
|
jmp common_exception
|
|
SYM_CODE_END(simd_coprocessor_error)
|
|
|
|
SYM_CODE_START(device_not_available)
|
|
ASM_CLAC
|
|
pushl $-1 # mark this as an int
|
|
pushl $do_device_not_available
|
|
jmp common_exception
|
|
SYM_CODE_END(device_not_available)
|
|
|
|
#ifdef CONFIG_PARAVIRT
|
|
SYM_CODE_START(native_iret)
|
|
iret
|
|
_ASM_EXTABLE(native_iret, iret_exc)
|
|
SYM_CODE_END(native_iret)
|
|
#endif
|
|
|
|
SYM_CODE_START(overflow)
|
|
ASM_CLAC
|
|
pushl $0
|
|
pushl $do_overflow
|
|
jmp common_exception
|
|
SYM_CODE_END(overflow)
|
|
|
|
SYM_CODE_START(bounds)
|
|
ASM_CLAC
|
|
pushl $0
|
|
pushl $do_bounds
|
|
jmp common_exception
|
|
SYM_CODE_END(bounds)
|
|
|
|
SYM_CODE_START(invalid_op)
|
|
ASM_CLAC
|
|
pushl $0
|
|
pushl $do_invalid_op
|
|
jmp common_exception
|
|
SYM_CODE_END(invalid_op)
|
|
|
|
SYM_CODE_START(coprocessor_segment_overrun)
|
|
ASM_CLAC
|
|
pushl $0
|
|
pushl $do_coprocessor_segment_overrun
|
|
jmp common_exception
|
|
SYM_CODE_END(coprocessor_segment_overrun)
|
|
|
|
SYM_CODE_START(invalid_TSS)
|
|
ASM_CLAC
|
|
pushl $do_invalid_TSS
|
|
jmp common_exception
|
|
SYM_CODE_END(invalid_TSS)
|
|
|
|
SYM_CODE_START(segment_not_present)
|
|
ASM_CLAC
|
|
pushl $do_segment_not_present
|
|
jmp common_exception
|
|
SYM_CODE_END(segment_not_present)
|
|
|
|
SYM_CODE_START(stack_segment)
|
|
ASM_CLAC
|
|
pushl $do_stack_segment
|
|
jmp common_exception
|
|
SYM_CODE_END(stack_segment)
|
|
|
|
SYM_CODE_START(alignment_check)
|
|
ASM_CLAC
|
|
pushl $do_alignment_check
|
|
jmp common_exception
|
|
SYM_CODE_END(alignment_check)
|
|
|
|
SYM_CODE_START(divide_error)
|
|
ASM_CLAC
|
|
pushl $0 # no error code
|
|
pushl $do_divide_error
|
|
jmp common_exception
|
|
SYM_CODE_END(divide_error)
|
|
|
|
#ifdef CONFIG_X86_MCE
|
|
SYM_CODE_START(machine_check)
|
|
ASM_CLAC
|
|
pushl $0
|
|
pushl machine_check_vector
|
|
jmp common_exception
|
|
SYM_CODE_END(machine_check)
|
|
#endif
|
|
|
|
SYM_CODE_START(spurious_interrupt_bug)
|
|
ASM_CLAC
|
|
pushl $0
|
|
pushl $do_spurious_interrupt_bug
|
|
jmp common_exception
|
|
SYM_CODE_END(spurious_interrupt_bug)
|
|
|
|
#ifdef CONFIG_XEN_PV
|
|
SYM_FUNC_START(xen_hypervisor_callback)
|
|
/*
|
|
* Check to see if we got the event in the critical
|
|
* region in xen_iret_direct, after we've reenabled
|
|
* events and checked for pending events. This simulates
|
|
* iret instruction's behaviour where it delivers a
|
|
* pending interrupt when enabling interrupts:
|
|
*/
|
|
cmpl $xen_iret_start_crit, (%esp)
|
|
jb 1f
|
|
cmpl $xen_iret_end_crit, (%esp)
|
|
jae 1f
|
|
call xen_iret_crit_fixup
|
|
1:
|
|
pushl $-1 /* orig_ax = -1 => not a system call */
|
|
SAVE_ALL
|
|
ENCODE_FRAME_POINTER
|
|
TRACE_IRQS_OFF
|
|
mov %esp, %eax
|
|
call xen_evtchn_do_upcall
|
|
#ifndef CONFIG_PREEMPTION
|
|
call xen_maybe_preempt_hcall
|
|
#endif
|
|
jmp ret_from_intr
|
|
SYM_FUNC_END(xen_hypervisor_callback)
|
|
|
|
/*
|
|
* Hypervisor uses this for application faults while it executes.
|
|
* We get here for two reasons:
|
|
* 1. Fault while reloading DS, ES, FS or GS
|
|
* 2. Fault while executing IRET
|
|
* Category 1 we fix up by reattempting the load, and zeroing the segment
|
|
* register if the load fails.
|
|
* Category 2 we fix up by jumping to do_iret_error. We cannot use the
|
|
* normal Linux return path in this case because if we use the IRET hypercall
|
|
* to pop the stack frame we end up in an infinite loop of failsafe callbacks.
|
|
* We distinguish between categories by maintaining a status value in EAX.
|
|
*/
|
|
SYM_FUNC_START(xen_failsafe_callback)
|
|
pushl %eax
|
|
movl $1, %eax
|
|
1: mov 4(%esp), %ds
|
|
2: mov 8(%esp), %es
|
|
3: mov 12(%esp), %fs
|
|
4: mov 16(%esp), %gs
|
|
/* EAX == 0 => Category 1 (Bad segment)
|
|
EAX != 0 => Category 2 (Bad IRET) */
|
|
testl %eax, %eax
|
|
popl %eax
|
|
lea 16(%esp), %esp
|
|
jz 5f
|
|
jmp iret_exc
|
|
5: pushl $-1 /* orig_ax = -1 => not a system call */
|
|
SAVE_ALL
|
|
ENCODE_FRAME_POINTER
|
|
jmp ret_from_exception
|
|
|
|
.section .fixup, "ax"
|
|
6: xorl %eax, %eax
|
|
movl %eax, 4(%esp)
|
|
jmp 1b
|
|
7: xorl %eax, %eax
|
|
movl %eax, 8(%esp)
|
|
jmp 2b
|
|
8: xorl %eax, %eax
|
|
movl %eax, 12(%esp)
|
|
jmp 3b
|
|
9: xorl %eax, %eax
|
|
movl %eax, 16(%esp)
|
|
jmp 4b
|
|
.previous
|
|
_ASM_EXTABLE(1b, 6b)
|
|
_ASM_EXTABLE(2b, 7b)
|
|
_ASM_EXTABLE(3b, 8b)
|
|
_ASM_EXTABLE(4b, 9b)
|
|
SYM_FUNC_END(xen_failsafe_callback)
|
|
#endif /* CONFIG_XEN_PV */
|
|
|
|
#ifdef CONFIG_XEN_PVHVM
|
|
BUILD_INTERRUPT3(xen_hvm_callback_vector, HYPERVISOR_CALLBACK_VECTOR,
|
|
xen_evtchn_do_upcall)
|
|
#endif
|
|
|
|
|
|
#if IS_ENABLED(CONFIG_HYPERV)
|
|
|
|
BUILD_INTERRUPT3(hyperv_callback_vector, HYPERVISOR_CALLBACK_VECTOR,
|
|
hyperv_vector_handler)
|
|
|
|
BUILD_INTERRUPT3(hyperv_reenlightenment_vector, HYPERV_REENLIGHTENMENT_VECTOR,
|
|
hyperv_reenlightenment_intr)
|
|
|
|
BUILD_INTERRUPT3(hv_stimer0_callback_vector, HYPERV_STIMER0_VECTOR,
|
|
hv_stimer0_vector_handler)
|
|
|
|
#endif /* CONFIG_HYPERV */
|
|
|
|
SYM_CODE_START(page_fault)
|
|
ASM_CLAC
|
|
pushl $do_page_fault
|
|
jmp common_exception_read_cr2
|
|
SYM_CODE_END(page_fault)
|
|
|
|
SYM_CODE_START_LOCAL_NOALIGN(common_exception_read_cr2)
|
|
/* the function address is in %gs's slot on the stack */
|
|
SAVE_ALL switch_stacks=1 skip_gs=1 unwind_espfix=1
|
|
|
|
ENCODE_FRAME_POINTER
|
|
|
|
/* fixup %gs */
|
|
GS_TO_REG %ecx
|
|
movl PT_GS(%esp), %edi
|
|
REG_TO_PTGS %ecx
|
|
SET_KERNEL_GS %ecx
|
|
|
|
GET_CR2_INTO(%ecx) # might clobber %eax
|
|
|
|
/* fixup orig %eax */
|
|
movl PT_ORIG_EAX(%esp), %edx # get the error code
|
|
movl $-1, PT_ORIG_EAX(%esp) # no syscall to restart
|
|
|
|
TRACE_IRQS_OFF
|
|
movl %esp, %eax # pt_regs pointer
|
|
CALL_NOSPEC %edi
|
|
jmp ret_from_exception
|
|
SYM_CODE_END(common_exception_read_cr2)
|
|
|
|
SYM_CODE_START_LOCAL_NOALIGN(common_exception)
|
|
/* the function address is in %gs's slot on the stack */
|
|
SAVE_ALL switch_stacks=1 skip_gs=1 unwind_espfix=1
|
|
ENCODE_FRAME_POINTER
|
|
|
|
/* fixup %gs */
|
|
GS_TO_REG %ecx
|
|
movl PT_GS(%esp), %edi # get the function address
|
|
REG_TO_PTGS %ecx
|
|
SET_KERNEL_GS %ecx
|
|
|
|
/* fixup orig %eax */
|
|
movl PT_ORIG_EAX(%esp), %edx # get the error code
|
|
movl $-1, PT_ORIG_EAX(%esp) # no syscall to restart
|
|
|
|
TRACE_IRQS_OFF
|
|
movl %esp, %eax # pt_regs pointer
|
|
CALL_NOSPEC %edi
|
|
jmp ret_from_exception
|
|
SYM_CODE_END(common_exception)
|
|
|
|
SYM_CODE_START(debug)
|
|
/*
|
|
* Entry from sysenter is now handled in common_exception
|
|
*/
|
|
ASM_CLAC
|
|
pushl $-1 # mark this as an int
|
|
pushl $do_debug
|
|
jmp common_exception
|
|
SYM_CODE_END(debug)
|
|
|
|
/*
|
|
* NMI is doubly nasty. It can happen on the first instruction of
|
|
* entry_SYSENTER_32 (just like #DB), but it can also interrupt the beginning
|
|
* of the #DB handler even if that #DB in turn hit before entry_SYSENTER_32
|
|
* switched stacks. We handle both conditions by simply checking whether we
|
|
* interrupted kernel code running on the SYSENTER stack.
|
|
*/
|
|
SYM_CODE_START(nmi)
|
|
ASM_CLAC
|
|
|
|
#ifdef CONFIG_X86_ESPFIX32
|
|
/*
|
|
* ESPFIX_SS is only ever set on the return to user path
|
|
* after we've switched to the entry stack.
|
|
*/
|
|
pushl %eax
|
|
movl %ss, %eax
|
|
cmpw $__ESPFIX_SS, %ax
|
|
popl %eax
|
|
je .Lnmi_espfix_stack
|
|
#endif
|
|
|
|
pushl %eax # pt_regs->orig_ax
|
|
SAVE_ALL_NMI cr3_reg=%edi
|
|
ENCODE_FRAME_POINTER
|
|
xorl %edx, %edx # zero error code
|
|
movl %esp, %eax # pt_regs pointer
|
|
|
|
/* Are we currently on the SYSENTER stack? */
|
|
movl PER_CPU_VAR(cpu_entry_area), %ecx
|
|
addl $CPU_ENTRY_AREA_entry_stack + SIZEOF_entry_stack, %ecx
|
|
subl %eax, %ecx /* ecx = (end of entry_stack) - esp */
|
|
cmpl $SIZEOF_entry_stack, %ecx
|
|
jb .Lnmi_from_sysenter_stack
|
|
|
|
/* Not on SYSENTER stack. */
|
|
call do_nmi
|
|
jmp .Lnmi_return
|
|
|
|
.Lnmi_from_sysenter_stack:
|
|
/*
|
|
* We're on the SYSENTER stack. Switch off. No one (not even debug)
|
|
* is using the thread stack right now, so it's safe for us to use it.
|
|
*/
|
|
movl %esp, %ebx
|
|
movl PER_CPU_VAR(cpu_current_top_of_stack), %esp
|
|
call do_nmi
|
|
movl %ebx, %esp
|
|
|
|
.Lnmi_return:
|
|
#ifdef CONFIG_X86_ESPFIX32
|
|
testl $CS_FROM_ESPFIX, PT_CS(%esp)
|
|
jnz .Lnmi_from_espfix
|
|
#endif
|
|
|
|
CHECK_AND_APPLY_ESPFIX
|
|
RESTORE_ALL_NMI cr3_reg=%edi pop=4
|
|
jmp .Lirq_return
|
|
|
|
#ifdef CONFIG_X86_ESPFIX32
|
|
.Lnmi_espfix_stack:
|
|
/*
|
|
* Create the pointer to LSS back
|
|
*/
|
|
pushl %ss
|
|
pushl %esp
|
|
addl $4, (%esp)
|
|
|
|
/* Copy the (short) IRET frame */
|
|
pushl 4*4(%esp) # flags
|
|
pushl 4*4(%esp) # cs
|
|
pushl 4*4(%esp) # ip
|
|
|
|
pushl %eax # orig_ax
|
|
|
|
SAVE_ALL_NMI cr3_reg=%edi unwind_espfix=1
|
|
ENCODE_FRAME_POINTER
|
|
|
|
/* clear CS_FROM_KERNEL, set CS_FROM_ESPFIX */
|
|
xorl $(CS_FROM_ESPFIX | CS_FROM_KERNEL), PT_CS(%esp)
|
|
|
|
xorl %edx, %edx # zero error code
|
|
movl %esp, %eax # pt_regs pointer
|
|
jmp .Lnmi_from_sysenter_stack
|
|
|
|
.Lnmi_from_espfix:
|
|
RESTORE_ALL_NMI cr3_reg=%edi
|
|
/*
|
|
* Because we cleared CS_FROM_KERNEL, IRET_FRAME 'forgot' to
|
|
* fix up the gap and long frame:
|
|
*
|
|
* 3 - original frame (exception)
|
|
* 2 - ESPFIX block (above)
|
|
* 6 - gap (FIXUP_FRAME)
|
|
* 5 - long frame (FIXUP_FRAME)
|
|
* 1 - orig_ax
|
|
*/
|
|
lss (1+5+6)*4(%esp), %esp # back to espfix stack
|
|
jmp .Lirq_return
|
|
#endif
|
|
SYM_CODE_END(nmi)
|
|
|
|
SYM_CODE_START(int3)
|
|
ASM_CLAC
|
|
pushl $-1 # mark this as an int
|
|
|
|
SAVE_ALL switch_stacks=1
|
|
ENCODE_FRAME_POINTER
|
|
TRACE_IRQS_OFF
|
|
xorl %edx, %edx # zero error code
|
|
movl %esp, %eax # pt_regs pointer
|
|
call do_int3
|
|
jmp ret_from_exception
|
|
SYM_CODE_END(int3)
|
|
|
|
SYM_CODE_START(general_protection)
|
|
pushl $do_general_protection
|
|
jmp common_exception
|
|
SYM_CODE_END(general_protection)
|
|
|
|
#ifdef CONFIG_KVM_GUEST
|
|
SYM_CODE_START(async_page_fault)
|
|
ASM_CLAC
|
|
pushl $do_async_page_fault
|
|
jmp common_exception_read_cr2
|
|
SYM_CODE_END(async_page_fault)
|
|
#endif
|
|
|
|
SYM_CODE_START(rewind_stack_do_exit)
|
|
/* Prevent any naive code from trying to unwind to our caller. */
|
|
xorl %ebp, %ebp
|
|
|
|
movl PER_CPU_VAR(cpu_current_top_of_stack), %esi
|
|
leal -TOP_OF_KERNEL_STACK_PADDING-PTREGS_SIZE(%esi), %esp
|
|
|
|
call do_exit
|
|
1: jmp 1b
|
|
SYM_CODE_END(rewind_stack_do_exit)
|