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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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d4f7423efd
The Hygon Dhyana CPU has a topology extensions bit in CPUID. With this bit, the kernel can get the cache information. So add support in cpuid4_cache_lookup_regs() to get the correct cache size. The Hygon Dhyana CPU also discovers num_cache_leaves via CPUID leaf 0x8000001d, so add support to it in find_num_cache_leaves(). Also add cacheinfo_hygon_init_llc_id() and init_hygon_cacheinfo() functions to initialize Dhyana cache info. Setup cache cpumap in the same way as AMD does. Signed-off-by: Pu Wen <puwen@hygon.cn> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Borislav Petkov <bp@suse.de> Cc: bp@alien8.de Cc: tglx@linutronix.de Cc: mingo@redhat.com Cc: hpa@zytor.com Cc: x86@kernel.org Cc: thomas.lendacky@amd.com Link: https://lkml.kernel.org/r/2a686b2ac0e2f5a1f2f5f101124d9dd44f949731.1537533369.git.puwen@hygon.cn
70 lines
2.1 KiB
C
70 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef ARCH_X86_CPU_H
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#define ARCH_X86_CPU_H
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/* attempt to consolidate cpu attributes */
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struct cpu_dev {
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const char *c_vendor;
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/* some have two possibilities for cpuid string */
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const char *c_ident[2];
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void (*c_early_init)(struct cpuinfo_x86 *);
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void (*c_bsp_init)(struct cpuinfo_x86 *);
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void (*c_init)(struct cpuinfo_x86 *);
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void (*c_identify)(struct cpuinfo_x86 *);
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void (*c_detect_tlb)(struct cpuinfo_x86 *);
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void (*c_bsp_resume)(struct cpuinfo_x86 *);
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int c_x86_vendor;
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#ifdef CONFIG_X86_32
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/* Optional vendor specific routine to obtain the cache size. */
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unsigned int (*legacy_cache_size)(struct cpuinfo_x86 *,
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unsigned int);
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/* Family/stepping-based lookup table for model names. */
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struct legacy_cpu_model_info {
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int family;
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const char *model_names[16];
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} legacy_models[5];
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#endif
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};
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struct _tlb_table {
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unsigned char descriptor;
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char tlb_type;
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unsigned int entries;
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/* unsigned int ways; */
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char info[128];
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};
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#define cpu_dev_register(cpu_devX) \
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static const struct cpu_dev *const __cpu_dev_##cpu_devX __used \
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__attribute__((__section__(".x86_cpu_dev.init"))) = \
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&cpu_devX;
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extern const struct cpu_dev *const __x86_cpu_dev_start[],
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*const __x86_cpu_dev_end[];
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extern void get_cpu_cap(struct cpuinfo_x86 *c);
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extern void get_cpu_address_sizes(struct cpuinfo_x86 *c);
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extern void cpu_detect_cache_sizes(struct cpuinfo_x86 *c);
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extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
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extern u32 get_scattered_cpuid_leaf(unsigned int level,
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unsigned int sub_leaf,
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enum cpuid_regs_idx reg);
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extern void init_intel_cacheinfo(struct cpuinfo_x86 *c);
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extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
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extern void init_hygon_cacheinfo(struct cpuinfo_x86 *c);
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extern void detect_num_cpu_cores(struct cpuinfo_x86 *c);
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extern int detect_extended_topology_early(struct cpuinfo_x86 *c);
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extern int detect_extended_topology(struct cpuinfo_x86 *c);
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extern int detect_ht_early(struct cpuinfo_x86 *c);
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extern void detect_ht(struct cpuinfo_x86 *c);
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unsigned int aperfmperf_get_khz(int cpu);
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extern void x86_spec_ctrl_setup_ap(void);
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#endif /* ARCH_X86_CPU_H */
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