mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-03 06:56:43 +07:00
2b40459b7e
Presently driver expects irq_gpio pin in platform data and maps it to irq itself. But we can also directly specify the interrupt in DT or platform file. Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
320 lines
8.8 KiB
C
320 lines
8.8 KiB
C
/*
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* max77686-irq.c - Interrupt controller support for MAX77686
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*
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* Copyright (C) 2012 Samsung Electronics Co.Ltd
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* Chiwoong Byun <woong.byun@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* This driver is based on max8997-irq.c
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*/
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#include <linux/err.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/gpio.h>
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#include <linux/mfd/max77686.h>
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#include <linux/mfd/max77686-private.h>
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#include <linux/irqdomain.h>
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#include <linux/regmap.h>
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enum {
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MAX77686_DEBUG_IRQ_INFO = 1 << 0,
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MAX77686_DEBUG_IRQ_MASK = 1 << 1,
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MAX77686_DEBUG_IRQ_INT = 1 << 2,
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};
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static int debug_mask = 0;
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module_param(debug_mask, int, 0);
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MODULE_PARM_DESC(debug_mask, "Set debug_mask : 0x0=off 0x1=IRQ_INFO 0x2=IRQ_MASK 0x4=IRQ_INI)");
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static const u8 max77686_mask_reg[] = {
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[PMIC_INT1] = MAX77686_REG_INT1MSK,
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[PMIC_INT2] = MAX77686_REG_INT2MSK,
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[RTC_INT] = MAX77686_RTC_INTM,
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};
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static struct regmap *max77686_get_regmap(struct max77686_dev *max77686,
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enum max77686_irq_source src)
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{
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switch (src) {
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case PMIC_INT1 ... PMIC_INT2:
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return max77686->regmap;
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case RTC_INT:
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return max77686->rtc_regmap;
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default:
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return ERR_PTR(-EINVAL);
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}
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}
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struct max77686_irq_data {
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int mask;
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enum max77686_irq_source group;
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};
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#define DECLARE_IRQ(idx, _group, _mask) \
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[(idx)] = { .group = (_group), .mask = (_mask) }
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static const struct max77686_irq_data max77686_irqs[] = {
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DECLARE_IRQ(MAX77686_PMICIRQ_PWRONF, PMIC_INT1, 1 << 0),
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DECLARE_IRQ(MAX77686_PMICIRQ_PWRONR, PMIC_INT1, 1 << 1),
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DECLARE_IRQ(MAX77686_PMICIRQ_JIGONBF, PMIC_INT1, 1 << 2),
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DECLARE_IRQ(MAX77686_PMICIRQ_JIGONBR, PMIC_INT1, 1 << 3),
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DECLARE_IRQ(MAX77686_PMICIRQ_ACOKBF, PMIC_INT1, 1 << 4),
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DECLARE_IRQ(MAX77686_PMICIRQ_ACOKBR, PMIC_INT1, 1 << 5),
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DECLARE_IRQ(MAX77686_PMICIRQ_ONKEY1S, PMIC_INT1, 1 << 6),
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DECLARE_IRQ(MAX77686_PMICIRQ_MRSTB, PMIC_INT1, 1 << 7),
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DECLARE_IRQ(MAX77686_PMICIRQ_140C, PMIC_INT2, 1 << 0),
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DECLARE_IRQ(MAX77686_PMICIRQ_120C, PMIC_INT2, 1 << 1),
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DECLARE_IRQ(MAX77686_RTCIRQ_RTC60S, RTC_INT, 1 << 0),
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DECLARE_IRQ(MAX77686_RTCIRQ_RTCA1, RTC_INT, 1 << 1),
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DECLARE_IRQ(MAX77686_RTCIRQ_RTCA2, RTC_INT, 1 << 2),
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DECLARE_IRQ(MAX77686_RTCIRQ_SMPL, RTC_INT, 1 << 3),
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DECLARE_IRQ(MAX77686_RTCIRQ_RTC1S, RTC_INT, 1 << 4),
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DECLARE_IRQ(MAX77686_RTCIRQ_WTSR, RTC_INT, 1 << 5),
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};
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static void max77686_irq_lock(struct irq_data *data)
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{
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struct max77686_dev *max77686 = irq_get_chip_data(data->irq);
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if (debug_mask & MAX77686_DEBUG_IRQ_MASK)
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pr_info("%s\n", __func__);
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mutex_lock(&max77686->irqlock);
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}
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static void max77686_irq_sync_unlock(struct irq_data *data)
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{
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struct max77686_dev *max77686 = irq_get_chip_data(data->irq);
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int i;
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for (i = 0; i < MAX77686_IRQ_GROUP_NR; i++) {
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u8 mask_reg = max77686_mask_reg[i];
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struct regmap *map = max77686_get_regmap(max77686, i);
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if (debug_mask & MAX77686_DEBUG_IRQ_MASK)
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pr_debug("%s: mask_reg[%d]=0x%x, cur=0x%x\n",
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__func__, i, mask_reg, max77686->irq_masks_cur[i]);
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if (mask_reg == MAX77686_REG_INVALID ||
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IS_ERR_OR_NULL(map))
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continue;
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max77686->irq_masks_cache[i] = max77686->irq_masks_cur[i];
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regmap_write(map, max77686_mask_reg[i],
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max77686->irq_masks_cur[i]);
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}
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mutex_unlock(&max77686->irqlock);
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}
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static const inline struct max77686_irq_data *to_max77686_irq(int irq)
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{
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struct irq_data *data = irq_get_irq_data(irq);
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return &max77686_irqs[data->hwirq];
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}
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static void max77686_irq_mask(struct irq_data *data)
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{
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struct max77686_dev *max77686 = irq_get_chip_data(data->irq);
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const struct max77686_irq_data *irq_data = to_max77686_irq(data->irq);
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max77686->irq_masks_cur[irq_data->group] |= irq_data->mask;
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if (debug_mask & MAX77686_DEBUG_IRQ_MASK)
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pr_info("%s: group=%d, cur=0x%x\n",
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__func__, irq_data->group,
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max77686->irq_masks_cur[irq_data->group]);
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}
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static void max77686_irq_unmask(struct irq_data *data)
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{
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struct max77686_dev *max77686 = irq_get_chip_data(data->irq);
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const struct max77686_irq_data *irq_data = to_max77686_irq(data->irq);
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max77686->irq_masks_cur[irq_data->group] &= ~irq_data->mask;
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if (debug_mask & MAX77686_DEBUG_IRQ_MASK)
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pr_info("%s: group=%d, cur=0x%x\n",
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__func__, irq_data->group,
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max77686->irq_masks_cur[irq_data->group]);
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}
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static struct irq_chip max77686_irq_chip = {
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.name = "max77686",
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.irq_bus_lock = max77686_irq_lock,
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.irq_bus_sync_unlock = max77686_irq_sync_unlock,
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.irq_mask = max77686_irq_mask,
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.irq_unmask = max77686_irq_unmask,
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};
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static irqreturn_t max77686_irq_thread(int irq, void *data)
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{
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struct max77686_dev *max77686 = data;
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unsigned int irq_reg[MAX77686_IRQ_GROUP_NR] = {};
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unsigned int irq_src;
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int ret;
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int i, cur_irq;
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ret = regmap_read(max77686->regmap, MAX77686_REG_INTSRC, &irq_src);
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if (ret < 0) {
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dev_err(max77686->dev, "Failed to read interrupt source: %d\n",
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ret);
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return IRQ_NONE;
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}
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if (debug_mask & MAX77686_DEBUG_IRQ_INT)
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pr_info("%s: irq_src=0x%x\n", __func__, irq_src);
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if (irq_src == MAX77686_IRQSRC_PMIC) {
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ret = regmap_bulk_read(max77686->regmap,
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MAX77686_REG_INT1, irq_reg, 2);
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if (ret < 0) {
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dev_err(max77686->dev, "Failed to read interrupt source: %d\n",
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ret);
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return IRQ_NONE;
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}
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if (debug_mask & MAX77686_DEBUG_IRQ_INT)
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pr_info("%s: int1=0x%x, int2=0x%x\n", __func__,
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irq_reg[PMIC_INT1], irq_reg[PMIC_INT2]);
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}
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if (irq_src & MAX77686_IRQSRC_RTC) {
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ret = regmap_read(max77686->rtc_regmap,
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MAX77686_RTC_INT, &irq_reg[RTC_INT]);
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if (ret < 0) {
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dev_err(max77686->dev, "Failed to read interrupt source: %d\n",
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ret);
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return IRQ_NONE;
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}
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if (debug_mask & MAX77686_DEBUG_IRQ_INT)
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pr_info("%s: rtc int=0x%x\n", __func__,
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irq_reg[RTC_INT]);
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}
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for (i = 0; i < MAX77686_IRQ_GROUP_NR; i++)
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irq_reg[i] &= ~max77686->irq_masks_cur[i];
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for (i = 0; i < MAX77686_IRQ_NR; i++) {
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if (irq_reg[max77686_irqs[i].group] & max77686_irqs[i].mask) {
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cur_irq = irq_find_mapping(max77686->irq_domain, i);
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if (cur_irq)
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handle_nested_irq(cur_irq);
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}
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}
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return IRQ_HANDLED;
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}
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static int max77686_irq_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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struct max77686_dev *max77686 = d->host_data;
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irq_set_chip_data(irq, max77686);
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irq_set_chip_and_handler(irq, &max77686_irq_chip, handle_edge_irq);
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irq_set_nested_thread(irq, 1);
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#ifdef CONFIG_ARM
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set_irq_flags(irq, IRQF_VALID);
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#else
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irq_set_noprobe(irq);
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#endif
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return 0;
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}
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static struct irq_domain_ops max77686_irq_domain_ops = {
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.map = max77686_irq_domain_map,
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};
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int max77686_irq_init(struct max77686_dev *max77686)
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{
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struct irq_domain *domain;
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int i;
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int ret;
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int val;
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struct regmap *map;
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mutex_init(&max77686->irqlock);
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if (max77686->irq_gpio && !max77686->irq) {
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max77686->irq = gpio_to_irq(max77686->irq_gpio);
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if (debug_mask & MAX77686_DEBUG_IRQ_INT) {
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ret = gpio_request(max77686->irq_gpio, "pmic_irq");
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if (ret < 0) {
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dev_err(max77686->dev,
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"Failed to request gpio %d with ret:"
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"%d\n", max77686->irq_gpio, ret);
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return IRQ_NONE;
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}
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gpio_direction_input(max77686->irq_gpio);
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val = gpio_get_value(max77686->irq_gpio);
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gpio_free(max77686->irq_gpio);
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pr_info("%s: gpio_irq=%x\n", __func__, val);
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}
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}
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if (!max77686->irq) {
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dev_err(max77686->dev, "irq is not specified\n");
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return -ENODEV;
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}
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/* Mask individual interrupt sources */
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for (i = 0; i < MAX77686_IRQ_GROUP_NR; i++) {
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max77686->irq_masks_cur[i] = 0xff;
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max77686->irq_masks_cache[i] = 0xff;
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map = max77686_get_regmap(max77686, i);
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if (IS_ERR_OR_NULL(map))
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continue;
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if (max77686_mask_reg[i] == MAX77686_REG_INVALID)
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continue;
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regmap_write(map, max77686_mask_reg[i], 0xff);
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}
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domain = irq_domain_add_linear(NULL, MAX77686_IRQ_NR,
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&max77686_irq_domain_ops, max77686);
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if (!domain) {
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dev_err(max77686->dev, "could not create irq domain\n");
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return -ENODEV;
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}
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max77686->irq_domain = domain;
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ret = request_threaded_irq(max77686->irq, NULL, max77686_irq_thread,
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IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
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"max77686-irq", max77686);
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if (ret)
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dev_err(max77686->dev, "Failed to request IRQ %d: %d\n",
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max77686->irq, ret);
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if (debug_mask & MAX77686_DEBUG_IRQ_INFO)
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pr_info("%s-\n", __func__);
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return 0;
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}
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void max77686_irq_exit(struct max77686_dev *max77686)
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{
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if (max77686->irq)
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free_irq(max77686->irq, max77686);
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}
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