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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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59d94d2ed4
On the Arria10, because of hardware bug, watchdog0 cannot reliably trigger a reset to the CPU. The workaround would be to use watchdog1 instead. Also for watchdog1, there is a dependency on the bootloader to enable the boot_clk source to be from the cb_intosc_hs_clk/2, versus from EOSC1. This corresponds to the (SWCTRLBTCLKEN & SWCTRLBTCLKSEL) bits enabled in the control register in the clock manager module of Arria10. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
166 lines
3.3 KiB
Plaintext
166 lines
3.3 KiB
Plaintext
/*
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* Copyright (C) 2015 Altera Corporation <www.altera.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "socfpga_arria10.dtsi"
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/ {
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model = "Altera SOCFPGA Arria 10";
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compatible = "altr,socfpga-arria10", "altr,socfpga";
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aliases {
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ethernet0 = &gmac0;
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serial0 = &uart1;
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};
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chosen {
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bootargs = "earlyprintk";
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stdout-path = "serial0:115200n8";
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};
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memory {
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name = "memory";
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device_type = "memory";
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reg = <0x0 0x40000000>; /* 1GB */
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};
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a10leds {
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compatible = "gpio-leds";
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a10sr_led0 {
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label = "a10sr-led0";
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gpios = <&a10sr_gpio 0 1>;
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};
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a10sr_led1 {
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label = "a10sr-led1";
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gpios = <&a10sr_gpio 1 1>;
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};
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a10sr_led2 {
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label = "a10sr-led2";
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gpios = <&a10sr_gpio 2 1>;
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};
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a10sr_led3 {
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label = "a10sr-led3";
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gpios = <&a10sr_gpio 3 1>;
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};
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};
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soc {
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clkmgr@ffd04000 {
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clocks {
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osc1 {
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clock-frequency = <25000000>;
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};
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};
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};
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};
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};
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&gmac0 {
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phy-mode = "rgmii";
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phy-addr = <0xffffffff>; /* probe for phy addr */
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/*
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* These skews assume the user's FPGA design is adding 600ps of delay
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* for TX_CLK on Arria 10.
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*
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* All skews are offset since hardware skew values for the ksz9031
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* range from a negative skew to a positive skew.
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* See the micrel-ksz90x1.txt Documentation file for details.
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*/
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txd0-skew-ps = <0>; /* -420ps */
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txd1-skew-ps = <0>; /* -420ps */
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txd2-skew-ps = <0>; /* -420ps */
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txd3-skew-ps = <0>; /* -420ps */
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rxd0-skew-ps = <420>; /* 0ps */
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rxd1-skew-ps = <420>; /* 0ps */
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rxd2-skew-ps = <420>; /* 0ps */
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rxd3-skew-ps = <420>; /* 0ps */
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txen-skew-ps = <0>; /* -420ps */
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txc-skew-ps = <1860>; /* 960ps */
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rxdv-skew-ps = <420>; /* 0ps */
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rxc-skew-ps = <1680>; /* 780ps */
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max-frame-size = <3800>;
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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&spi1 {
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status = "okay";
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resource-manager@0 {
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compatible = "altr,a10sr";
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reg = <0>;
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spi-max-frequency = <100000>;
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/* low-level active IRQ at GPIO1_5 */
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interrupt-parent = <&portb>;
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interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
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interrupt-controller;
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#interrupt-cells = <2>;
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a10sr_gpio: gpio-controller {
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compatible = "altr,a10sr-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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};
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&i2c1 {
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speed-mode = <0>;
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status = "okay";
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/*
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* adjust the falling times to decrease the i2c frequency to 50Khz
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* because the LCD module does not work at the standard 100Khz
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*/
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i2c-sda-falling-time-ns = <6000>;
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i2c-scl-falling-time-ns = <6000>;
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eeprom@51 {
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compatible = "atmel,24c32";
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reg = <0x51>;
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pagesize = <32>;
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};
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rtc@68 {
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compatible = "dallas,ds1339";
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reg = <0x68>;
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};
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ltc@5c {
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compatible = "ltc2977";
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reg = <0x5c>;
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};
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};
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&uart1 {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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};
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&watchdog1 {
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status = "okay";
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};
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