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ARC AXS10x boards support custom IP-block which allows to control reset signals of selected peripherals. For example DW GMAC, etc... This block is controlled via memory-mapped register (AKA CREG) which represents up-to 32 reset lines. This regiter is self-clearing so we don't need to deassert line after reset. As of today only the following lines are used: - DW GMAC - line 5 Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
34 lines
922 B
Plaintext
34 lines
922 B
Plaintext
Binding for the AXS10x reset controller
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This binding describes the ARC AXS10x boards custom IP-block which allows
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to control reset signals of selected peripherals. For example DW GMAC, etc...
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This block is controlled via memory-mapped register (AKA CREG) which
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represents up-to 32 reset lines.
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As of today only the following lines are used:
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- DW GMAC - line 5
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This binding uses the common reset binding[1].
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[1] Documentation/devicetree/bindings/reset/reset.txt
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Required properties:
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- compatible: should be "snps,axs10x-reset".
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- reg: should always contain pair address - length: for creg reset
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bits register.
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- #reset-cells: from common reset binding; Should always be set to 1.
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Example:
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reset: reset-controller@11220 {
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compatible = "snps,axs10x-reset";
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#reset-cells = <1>;
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reg = <0x11220 0x4>;
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};
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Specifying reset lines connected to IP modules:
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ethernet@.... {
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....
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resets = <&reset 5>;
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....
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};
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