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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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e9cbf6299e
Building an MSA capable kernel with a toolchain that supports MSA
produces warnings such as this:
CC arch/mips/kernel/cpu-probe.o
{standard input}: Assembler messages:
{standard input}:4786: Warning: the `msa' extension requires 64-bit FPRs
This is due to ".set msa" without ".set fp=64" in the inline assembly of
control register accessors, since MSA requires the 64-bit FPU registers
(FR=1). Add the missing fp=64 in these functions to silence the
warnings.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13554/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
308 lines
8.0 KiB
C
308 lines
8.0 KiB
C
/*
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* Copyright (C) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef _ASM_MSA_H
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#define _ASM_MSA_H
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#include <asm/mipsregs.h>
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#ifndef __ASSEMBLY__
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#include <asm/inst.h>
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extern void _save_msa(struct task_struct *);
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extern void _restore_msa(struct task_struct *);
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extern void _init_msa_upper(void);
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extern void read_msa_wr_b(unsigned idx, union fpureg *to);
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extern void read_msa_wr_h(unsigned idx, union fpureg *to);
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extern void read_msa_wr_w(unsigned idx, union fpureg *to);
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extern void read_msa_wr_d(unsigned idx, union fpureg *to);
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/**
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* read_msa_wr() - Read a single MSA vector register
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* @idx: The index of the vector register to read
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* @to: The FPU register union to store the registers value in
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* @fmt: The format of the data in the vector register
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*
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* Read the value of MSA vector register idx into the FPU register
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* union to, using the format fmt.
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*/
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static inline void read_msa_wr(unsigned idx, union fpureg *to,
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enum msa_2b_fmt fmt)
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{
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switch (fmt) {
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case msa_fmt_b:
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read_msa_wr_b(idx, to);
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break;
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case msa_fmt_h:
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read_msa_wr_h(idx, to);
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break;
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case msa_fmt_w:
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read_msa_wr_w(idx, to);
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break;
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case msa_fmt_d:
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read_msa_wr_d(idx, to);
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break;
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default:
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BUG();
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}
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}
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extern void write_msa_wr_b(unsigned idx, union fpureg *from);
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extern void write_msa_wr_h(unsigned idx, union fpureg *from);
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extern void write_msa_wr_w(unsigned idx, union fpureg *from);
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extern void write_msa_wr_d(unsigned idx, union fpureg *from);
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/**
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* write_msa_wr() - Write a single MSA vector register
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* @idx: The index of the vector register to write
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* @from: The FPU register union to take the registers value from
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* @fmt: The format of the data in the vector register
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*
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* Write the value from the FPU register union from into MSA vector
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* register idx, using the format fmt.
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*/
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static inline void write_msa_wr(unsigned idx, union fpureg *from,
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enum msa_2b_fmt fmt)
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{
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switch (fmt) {
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case msa_fmt_b:
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write_msa_wr_b(idx, from);
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break;
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case msa_fmt_h:
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write_msa_wr_h(idx, from);
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break;
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case msa_fmt_w:
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write_msa_wr_w(idx, from);
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break;
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case msa_fmt_d:
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write_msa_wr_d(idx, from);
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break;
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default:
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BUG();
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}
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}
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static inline void enable_msa(void)
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{
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if (cpu_has_msa) {
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set_c0_config5(MIPS_CONF5_MSAEN);
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enable_fpu_hazard();
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}
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}
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static inline void disable_msa(void)
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{
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if (cpu_has_msa) {
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clear_c0_config5(MIPS_CONF5_MSAEN);
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disable_fpu_hazard();
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}
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}
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static inline int is_msa_enabled(void)
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{
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if (!cpu_has_msa)
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return 0;
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return read_c0_config5() & MIPS_CONF5_MSAEN;
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}
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static inline int thread_msa_context_live(void)
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{
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/*
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* Check cpu_has_msa only if it's a constant. This will allow the
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* compiler to optimise out code for CPUs without MSA without adding
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* an extra redundant check for CPUs with MSA.
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*/
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if (__builtin_constant_p(cpu_has_msa) && !cpu_has_msa)
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return 0;
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return test_thread_flag(TIF_MSA_CTX_LIVE);
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}
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static inline void save_msa(struct task_struct *t)
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{
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if (cpu_has_msa)
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_save_msa(t);
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}
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static inline void restore_msa(struct task_struct *t)
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{
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if (cpu_has_msa)
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_restore_msa(t);
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}
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static inline void init_msa_upper(void)
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{
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/*
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* Check cpu_has_msa only if it's a constant. This will allow the
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* compiler to optimise out code for CPUs without MSA without adding
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* an extra redundant check for CPUs with MSA.
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*/
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if (__builtin_constant_p(cpu_has_msa) && !cpu_has_msa)
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return;
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_init_msa_upper();
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}
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#ifdef TOOLCHAIN_SUPPORTS_MSA
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#define __BUILD_MSA_CTL_REG(name, cs) \
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static inline unsigned int read_msa_##name(void) \
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{ \
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unsigned int reg; \
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__asm__ __volatile__( \
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" .set push\n" \
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" .set fp=64\n" \
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" .set msa\n" \
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" cfcmsa %0, $" #cs "\n" \
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" .set pop\n" \
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: "=r"(reg)); \
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return reg; \
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} \
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\
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static inline void write_msa_##name(unsigned int val) \
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{ \
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__asm__ __volatile__( \
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" .set push\n" \
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" .set fp=64\n" \
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" .set msa\n" \
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" ctcmsa $" #cs ", %0\n" \
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" .set pop\n" \
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: : "r"(val)); \
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}
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#else /* !TOOLCHAIN_SUPPORTS_MSA */
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/*
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* Define functions using .word for the c[ft]cmsa instructions in order to
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* allow compilation with toolchains that do not support MSA. Once all
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* toolchains in use support MSA these can be removed.
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*/
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#define __BUILD_MSA_CTL_REG(name, cs) \
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static inline unsigned int read_msa_##name(void) \
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{ \
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unsigned int reg; \
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__asm__ __volatile__( \
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" .set push\n" \
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" .set noat\n" \
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" # cfcmsa $1, $%1\n" \
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_ASM_INSN_IF_MIPS(0x787e0059 | %1 << 11) \
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_ASM_INSN32_IF_MM(0x587e0056 | %1 << 11) \
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" move %0, $1\n" \
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" .set pop\n" \
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: "=r"(reg) : "i"(cs)); \
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return reg; \
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} \
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\
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static inline void write_msa_##name(unsigned int val) \
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{ \
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__asm__ __volatile__( \
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" .set push\n" \
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" .set noat\n" \
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" move $1, %0\n" \
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" # ctcmsa $%1, $1\n" \
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_ASM_INSN_IF_MIPS(0x783e0819 | %1 << 6) \
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_ASM_INSN32_IF_MM(0x583e0816 | %1 << 6) \
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" .set pop\n" \
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: : "r"(val), "i"(cs)); \
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}
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#endif /* !TOOLCHAIN_SUPPORTS_MSA */
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__BUILD_MSA_CTL_REG(ir, 0)
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__BUILD_MSA_CTL_REG(csr, 1)
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__BUILD_MSA_CTL_REG(access, 2)
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__BUILD_MSA_CTL_REG(save, 3)
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__BUILD_MSA_CTL_REG(modify, 4)
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__BUILD_MSA_CTL_REG(request, 5)
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__BUILD_MSA_CTL_REG(map, 6)
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__BUILD_MSA_CTL_REG(unmap, 7)
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#endif /* !__ASSEMBLY__ */
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#define MSA_IR 0
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#define MSA_CSR 1
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#define MSA_ACCESS 2
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#define MSA_SAVE 3
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#define MSA_MODIFY 4
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#define MSA_REQUEST 5
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#define MSA_MAP 6
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#define MSA_UNMAP 7
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/* MSA Implementation Register (MSAIR) */
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#define MSA_IR_REVB 0
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#define MSA_IR_REVF (_ULCAST_(0xff) << MSA_IR_REVB)
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#define MSA_IR_PROCB 8
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#define MSA_IR_PROCF (_ULCAST_(0xff) << MSA_IR_PROCB)
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#define MSA_IR_WRPB 16
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#define MSA_IR_WRPF (_ULCAST_(0x1) << MSA_IR_WRPB)
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/* MSA Control & Status Register (MSACSR) */
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#define MSA_CSR_RMB 0
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#define MSA_CSR_RMF (_ULCAST_(0x3) << MSA_CSR_RMB)
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#define MSA_CSR_RM_NEAREST 0
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#define MSA_CSR_RM_TO_ZERO 1
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#define MSA_CSR_RM_TO_POS 2
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#define MSA_CSR_RM_TO_NEG 3
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#define MSA_CSR_FLAGSB 2
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#define MSA_CSR_FLAGSF (_ULCAST_(0x1f) << MSA_CSR_FLAGSB)
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#define MSA_CSR_FLAGS_IB 2
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#define MSA_CSR_FLAGS_IF (_ULCAST_(0x1) << MSA_CSR_FLAGS_IB)
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#define MSA_CSR_FLAGS_UB 3
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#define MSA_CSR_FLAGS_UF (_ULCAST_(0x1) << MSA_CSR_FLAGS_UB)
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#define MSA_CSR_FLAGS_OB 4
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#define MSA_CSR_FLAGS_OF (_ULCAST_(0x1) << MSA_CSR_FLAGS_OB)
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#define MSA_CSR_FLAGS_ZB 5
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#define MSA_CSR_FLAGS_ZF (_ULCAST_(0x1) << MSA_CSR_FLAGS_ZB)
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#define MSA_CSR_FLAGS_VB 6
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#define MSA_CSR_FLAGS_VF (_ULCAST_(0x1) << MSA_CSR_FLAGS_VB)
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#define MSA_CSR_ENABLESB 7
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#define MSA_CSR_ENABLESF (_ULCAST_(0x1f) << MSA_CSR_ENABLESB)
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#define MSA_CSR_ENABLES_IB 7
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#define MSA_CSR_ENABLES_IF (_ULCAST_(0x1) << MSA_CSR_ENABLES_IB)
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#define MSA_CSR_ENABLES_UB 8
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#define MSA_CSR_ENABLES_UF (_ULCAST_(0x1) << MSA_CSR_ENABLES_UB)
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#define MSA_CSR_ENABLES_OB 9
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#define MSA_CSR_ENABLES_OF (_ULCAST_(0x1) << MSA_CSR_ENABLES_OB)
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#define MSA_CSR_ENABLES_ZB 10
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#define MSA_CSR_ENABLES_ZF (_ULCAST_(0x1) << MSA_CSR_ENABLES_ZB)
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#define MSA_CSR_ENABLES_VB 11
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#define MSA_CSR_ENABLES_VF (_ULCAST_(0x1) << MSA_CSR_ENABLES_VB)
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#define MSA_CSR_CAUSEB 12
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#define MSA_CSR_CAUSEF (_ULCAST_(0x3f) << MSA_CSR_CAUSEB)
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#define MSA_CSR_CAUSE_IB 12
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#define MSA_CSR_CAUSE_IF (_ULCAST_(0x1) << MSA_CSR_CAUSE_IB)
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#define MSA_CSR_CAUSE_UB 13
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#define MSA_CSR_CAUSE_UF (_ULCAST_(0x1) << MSA_CSR_CAUSE_UB)
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#define MSA_CSR_CAUSE_OB 14
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#define MSA_CSR_CAUSE_OF (_ULCAST_(0x1) << MSA_CSR_CAUSE_OB)
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#define MSA_CSR_CAUSE_ZB 15
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#define MSA_CSR_CAUSE_ZF (_ULCAST_(0x1) << MSA_CSR_CAUSE_ZB)
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#define MSA_CSR_CAUSE_VB 16
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#define MSA_CSR_CAUSE_VF (_ULCAST_(0x1) << MSA_CSR_CAUSE_VB)
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#define MSA_CSR_CAUSE_EB 17
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#define MSA_CSR_CAUSE_EF (_ULCAST_(0x1) << MSA_CSR_CAUSE_EB)
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#define MSA_CSR_NXB 18
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#define MSA_CSR_NXF (_ULCAST_(0x1) << MSA_CSR_NXB)
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#define MSA_CSR_FSB 24
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#define MSA_CSR_FSF (_ULCAST_(0x1) << MSA_CSR_FSB)
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#endif /* _ASM_MSA_H */
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