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Add the definitions of sync stype 0 (global completion barrier) and sync stype 0x10 (local ordering barrier) to barrier.h for use with the sync instruction. These types are defined by the MIPS Instruction Set since R2 of the architecture and are documented in document MD00087 table 6.5. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14222/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
228 lines
8.0 KiB
C
228 lines
8.0 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2006 by Ralf Baechle (ralf@linux-mips.org)
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*/
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#ifndef __ASM_BARRIER_H
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#define __ASM_BARRIER_H
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#include <asm/addrspace.h>
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/*
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* Sync types defined by the MIPS architecture (document MD00087 table 6.5)
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* These values are used with the sync instruction to perform memory barriers.
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* Types of ordering guarantees available through the SYNC instruction:
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* - Completion Barriers
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* - Ordering Barriers
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* As compared to the completion barrier, the ordering barrier is a
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* lighter-weight operation as it does not require the specified instructions
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* before the SYNC to be already completed. Instead it only requires that those
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* specified instructions which are subsequent to the SYNC in the instruction
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* stream are never re-ordered for processing ahead of the specified
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* instructions which are before the SYNC in the instruction stream.
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* This potentially reduces how many cycles the barrier instruction must stall
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* before it completes.
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* Implementations that do not use any of the non-zero values of stype to define
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* different barriers, such as ordering barriers, must make those stype values
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* act the same as stype zero.
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*/
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/*
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* Completion barriers:
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* - Every synchronizable specified memory instruction (loads or stores or both)
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* that occurs in the instruction stream before the SYNC instruction must be
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* already globally performed before any synchronizable specified memory
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* instructions that occur after the SYNC are allowed to be performed, with
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* respect to any other processor or coherent I/O module.
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*
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* - The barrier does not guarantee the order in which instruction fetches are
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* performed.
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*
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* - A stype value of zero will always be defined such that it performs the most
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* complete set of synchronization operations that are defined.This means
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* stype zero always does a completion barrier that affects both loads and
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* stores preceding the SYNC instruction and both loads and stores that are
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* subsequent to the SYNC instruction. Non-zero values of stype may be defined
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* by the architecture or specific implementations to perform synchronization
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* behaviors that are less complete than that of stype zero. If an
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* implementation does not use one of these non-zero values to define a
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* different synchronization behavior, then that non-zero value of stype must
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* act the same as stype zero completion barrier. This allows software written
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* for an implementation with a lighter-weight barrier to work on another
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* implementation which only implements the stype zero completion barrier.
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*
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* - A completion barrier is required, potentially in conjunction with SSNOP (in
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* Release 1 of the Architecture) or EHB (in Release 2 of the Architecture),
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* to guarantee that memory reference results are visible across operating
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* mode changes. For example, a completion barrier is required on some
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* implementations on entry to and exit from Debug Mode to guarantee that
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* memory effects are handled correctly.
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*/
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/*
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* stype 0 - A completion barrier that affects preceding loads and stores and
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* subsequent loads and stores.
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* Older instructions which must reach the load/store ordering point before the
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* SYNC instruction completes: Loads, Stores
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* Younger instructions which must reach the load/store ordering point only
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* after the SYNC instruction completes: Loads, Stores
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* Older instructions which must be globally performed when the SYNC instruction
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* completes: Loads, Stores
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*/
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#define STYPE_SYNC 0x0
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/*
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* Ordering barriers:
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* - Every synchronizable specified memory instruction (loads or stores or both)
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* that occurs in the instruction stream before the SYNC instruction must
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* reach a stage in the load/store datapath after which no instruction
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* re-ordering is possible before any synchronizable specified memory
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* instruction which occurs after the SYNC instruction in the instruction
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* stream reaches the same stage in the load/store datapath.
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*
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* - If any memory instruction before the SYNC instruction in program order,
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* generates a memory request to the external memory and any memory
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* instruction after the SYNC instruction in program order also generates a
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* memory request to external memory, the memory request belonging to the
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* older instruction must be globally performed before the time the memory
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* request belonging to the younger instruction is globally performed.
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*
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* - The barrier does not guarantee the order in which instruction fetches are
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* performed.
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*/
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/*
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* stype 0x10 - An ordering barrier that affects preceding loads and stores and
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* subsequent loads and stores.
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* Older instructions which must reach the load/store ordering point before the
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* SYNC instruction completes: Loads, Stores
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* Younger instructions which must reach the load/store ordering point only
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* after the SYNC instruction completes: Loads, Stores
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* Older instructions which must be globally performed when the SYNC instruction
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* completes: N/A
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*/
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#define STYPE_SYNC_MB 0x10
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#ifdef CONFIG_CPU_HAS_SYNC
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#define __sync() \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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".set mips2\n\t" \
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"sync\n\t" \
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".set pop" \
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: /* no output */ \
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: /* no input */ \
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: "memory")
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#else
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#define __sync() do { } while(0)
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#endif
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#define __fast_iob() \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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"lw $0,%0\n\t" \
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"nop\n\t" \
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".set pop" \
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: /* no output */ \
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: "m" (*(int *)CKSEG1) \
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: "memory")
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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# define OCTEON_SYNCW_STR ".set push\n.set arch=octeon\nsyncw\nsyncw\n.set pop\n"
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# define __syncw() __asm__ __volatile__(OCTEON_SYNCW_STR : : : "memory")
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# define fast_wmb() __syncw()
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# define fast_rmb() barrier()
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# define fast_mb() __sync()
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# define fast_iob() do { } while (0)
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#else /* ! CONFIG_CPU_CAVIUM_OCTEON */
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# define fast_wmb() __sync()
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# define fast_rmb() __sync()
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# define fast_mb() __sync()
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# ifdef CONFIG_SGI_IP28
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# define fast_iob() \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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"lw $0,%0\n\t" \
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"sync\n\t" \
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"lw $0,%0\n\t" \
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".set pop" \
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: /* no output */ \
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: "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \
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: "memory")
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# else
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# define fast_iob() \
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do { \
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__sync(); \
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__fast_iob(); \
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} while (0)
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# endif
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#endif /* CONFIG_CPU_CAVIUM_OCTEON */
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#ifdef CONFIG_CPU_HAS_WB
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#include <asm/wbflush.h>
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#define mb() wbflush()
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#define iob() wbflush()
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#else /* !CONFIG_CPU_HAS_WB */
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#define mb() fast_mb()
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#define iob() fast_iob()
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#endif /* !CONFIG_CPU_HAS_WB */
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#define wmb() fast_wmb()
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#define rmb() fast_rmb()
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#if defined(CONFIG_WEAK_ORDERING)
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# ifdef CONFIG_CPU_CAVIUM_OCTEON
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# define __smp_mb() __sync()
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# define __smp_rmb() barrier()
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# define __smp_wmb() __syncw()
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# else
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# define __smp_mb() __asm__ __volatile__("sync" : : :"memory")
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# define __smp_rmb() __asm__ __volatile__("sync" : : :"memory")
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# define __smp_wmb() __asm__ __volatile__("sync" : : :"memory")
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# endif
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#else
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#define __smp_mb() barrier()
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#define __smp_rmb() barrier()
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#define __smp_wmb() barrier()
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#endif
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#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)
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#define __WEAK_LLSC_MB " sync \n"
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#else
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#define __WEAK_LLSC_MB " \n"
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#endif
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#define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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#define smp_mb__before_llsc() smp_wmb()
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#define __smp_mb__before_llsc() __smp_wmb()
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/* Cause previous writes to become visible on all CPUs as soon as possible */
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#define nudge_writes() __asm__ __volatile__(".set push\n\t" \
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".set arch=octeon\n\t" \
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"syncw\n\t" \
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".set pop" : : : "memory")
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#else
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#define smp_mb__before_llsc() smp_llsc_mb()
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#define __smp_mb__before_llsc() smp_llsc_mb()
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#define nudge_writes() mb()
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#endif
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#define __smp_mb__before_atomic() __smp_mb__before_llsc()
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#define __smp_mb__after_atomic() smp_llsc_mb()
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#include <asm-generic/barrier.h>
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#endif /* __ASM_BARRIER_H */
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