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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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845d6b0ff9
Some clock gates have a pre-divider between the source input and the gate itself. A notable example is the HSIC 12 MHz clock found on the A83T, which has the 24 MHz main oscillator as its input, and a /2 pre-divider. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
130 lines
2.9 KiB
C
130 lines
2.9 KiB
C
/*
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* Copyright (C) 2016 Maxime Ripard
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <linux/clk-provider.h>
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#include "ccu_gate.h"
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void ccu_gate_helper_disable(struct ccu_common *common, u32 gate)
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{
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unsigned long flags;
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u32 reg;
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if (!gate)
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return;
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spin_lock_irqsave(common->lock, flags);
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reg = readl(common->base + common->reg);
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writel(reg & ~gate, common->base + common->reg);
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spin_unlock_irqrestore(common->lock, flags);
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}
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static void ccu_gate_disable(struct clk_hw *hw)
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{
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struct ccu_gate *cg = hw_to_ccu_gate(hw);
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return ccu_gate_helper_disable(&cg->common, cg->enable);
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}
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int ccu_gate_helper_enable(struct ccu_common *common, u32 gate)
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{
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unsigned long flags;
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u32 reg;
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if (!gate)
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return 0;
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spin_lock_irqsave(common->lock, flags);
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reg = readl(common->base + common->reg);
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writel(reg | gate, common->base + common->reg);
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spin_unlock_irqrestore(common->lock, flags);
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return 0;
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}
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static int ccu_gate_enable(struct clk_hw *hw)
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{
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struct ccu_gate *cg = hw_to_ccu_gate(hw);
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return ccu_gate_helper_enable(&cg->common, cg->enable);
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}
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int ccu_gate_helper_is_enabled(struct ccu_common *common, u32 gate)
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{
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if (!gate)
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return 1;
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return readl(common->base + common->reg) & gate;
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}
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static int ccu_gate_is_enabled(struct clk_hw *hw)
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{
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struct ccu_gate *cg = hw_to_ccu_gate(hw);
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return ccu_gate_helper_is_enabled(&cg->common, cg->enable);
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}
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static unsigned long ccu_gate_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct ccu_gate *cg = hw_to_ccu_gate(hw);
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unsigned long rate = parent_rate;
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if (cg->common.features & CCU_FEATURE_ALL_PREDIV)
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rate /= cg->common.prediv;
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return rate;
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}
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static long ccu_gate_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct ccu_gate *cg = hw_to_ccu_gate(hw);
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int div = 1;
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if (cg->common.features & CCU_FEATURE_ALL_PREDIV)
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div = cg->common.prediv;
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if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
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unsigned long best_parent = rate;
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if (cg->common.features & CCU_FEATURE_ALL_PREDIV)
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best_parent *= div;
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*prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
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}
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return *prate / div;
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}
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static int ccu_gate_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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/*
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* We must report success but we can do so unconditionally because
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* clk_factor_round_rate returns values that ensure this call is a
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* nop.
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*/
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return 0;
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}
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const struct clk_ops ccu_gate_ops = {
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.disable = ccu_gate_disable,
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.enable = ccu_gate_enable,
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.is_enabled = ccu_gate_is_enabled,
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.round_rate = ccu_gate_round_rate,
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.set_rate = ccu_gate_set_rate,
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.recalc_rate = ccu_gate_recalc_rate,
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};
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