mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 11:58:21 +07:00
4053aa65c5
Utilize common Tegra30 CPU OPP table. CPU DVFS is available now on Cardhu A04. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
155 lines
3.6 KiB
Plaintext
155 lines
3.6 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
|
|
/dts-v1/;
|
|
|
|
#include "tegra30-cardhu.dtsi"
|
|
#include "tegra30-cpu-opp.dtsi"
|
|
#include "tegra30-cpu-opp-microvolt.dtsi"
|
|
|
|
/* This dts file support the cardhu A04 and later versions of board */
|
|
|
|
/ {
|
|
model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board";
|
|
compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30";
|
|
|
|
sdhci@78000400 {
|
|
status = "okay";
|
|
power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
|
|
bus-width = <4>;
|
|
keep-power-in-suspend;
|
|
};
|
|
|
|
regulators {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
ddr_reg: regulator@100 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "ddr";
|
|
reg = <100>;
|
|
regulator-min-microvolt = <1500000>;
|
|
regulator-max-microvolt = <1500000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
enable-active-high;
|
|
gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
sys_3v3_reg: regulator@101 {
|
|
compatible = "regulator-fixed";
|
|
reg = <101>;
|
|
regulator-name = "sys_3v3";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
enable-active-high;
|
|
gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
usb1_vbus_reg: regulator@102 {
|
|
compatible = "regulator-fixed";
|
|
reg = <102>;
|
|
regulator-name = "usb1_vbus";
|
|
regulator-min-microvolt = <5000000>;
|
|
regulator-max-microvolt = <5000000>;
|
|
enable-active-high;
|
|
gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
|
|
gpio-open-drain;
|
|
vin-supply = <&vdd_5v0_reg>;
|
|
};
|
|
|
|
usb3_vbus_reg: regulator@103 {
|
|
compatible = "regulator-fixed";
|
|
reg = <103>;
|
|
regulator-name = "usb3_vbus";
|
|
regulator-min-microvolt = <5000000>;
|
|
regulator-max-microvolt = <5000000>;
|
|
enable-active-high;
|
|
gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
|
|
gpio-open-drain;
|
|
vin-supply = <&vdd_5v0_reg>;
|
|
};
|
|
|
|
vdd_5v0_reg: regulator@104 {
|
|
compatible = "regulator-fixed";
|
|
reg = <104>;
|
|
regulator-name = "5v0";
|
|
regulator-min-microvolt = <5000000>;
|
|
regulator-max-microvolt = <5000000>;
|
|
enable-active-high;
|
|
gpio = <&pmic 8 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
vdd_bl_reg: regulator@105 {
|
|
compatible = "regulator-fixed";
|
|
reg = <105>;
|
|
regulator-name = "vdd_bl";
|
|
regulator-min-microvolt = <5000000>;
|
|
regulator-max-microvolt = <5000000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
enable-active-high;
|
|
gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
vdd_bl2_reg: regulator@106 {
|
|
compatible = "regulator-fixed";
|
|
reg = <106>;
|
|
regulator-name = "vdd_bl2";
|
|
regulator-min-microvolt = <5000000>;
|
|
regulator-max-microvolt = <5000000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
enable-active-high;
|
|
gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
|
|
};
|
|
};
|
|
|
|
i2c@7000d000 {
|
|
pmic: tps65911@2d {
|
|
regulators {
|
|
vddctrl_reg: vddctrl {
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <1125000>;
|
|
regulator-coupled-with = <&vddcore_reg>;
|
|
regulator-coupled-max-spread = <300000>;
|
|
regulator-max-step-microvolt = <100000>;
|
|
|
|
nvidia,tegra-cpu-regulator;
|
|
};
|
|
};
|
|
};
|
|
|
|
vddcore_reg: tps62361@60 {
|
|
regulator-coupled-with = <&vddctrl_reg>;
|
|
regulator-coupled-max-spread = <300000>;
|
|
regulator-max-step-microvolt = <100000>;
|
|
|
|
nvidia,tegra-core-regulator;
|
|
};
|
|
};
|
|
|
|
cpus {
|
|
cpu0: cpu@0 {
|
|
cpu-supply = <&vddctrl_reg>;
|
|
operating-points-v2 = <&cpu0_opp_table>;
|
|
};
|
|
|
|
cpu@1 {
|
|
cpu-supply = <&vddctrl_reg>;
|
|
operating-points-v2 = <&cpu0_opp_table>;
|
|
};
|
|
|
|
cpu@2 {
|
|
cpu-supply = <&vddctrl_reg>;
|
|
operating-points-v2 = <&cpu0_opp_table>;
|
|
};
|
|
|
|
cpu@3 {
|
|
cpu-supply = <&vddctrl_reg>;
|
|
operating-points-v2 = <&cpu0_opp_table>;
|
|
};
|
|
};
|
|
};
|