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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
30ad29bb48
Currently, code of Loongson-2/3 is under loongson directory and code of Loongson-1 is under loongson1 directory. Besides, there are Kconfig options such as MACH_LOONGSON and MACH_LOONGSON1. This naming style is very ugly and confusing. Since Loongson-2/3 are both 64-bit general- purpose CPU while Loongson-1 is 32-bit SoC, we rename both file names and Kconfig symbols from loongson/loongson1 to loongson64/loongson32. [ralf@linux-mips.org: Resolve a number of simple conflicts.] Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Kelvin Cheung <keguang.zhang@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/9790/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
51 lines
1.3 KiB
C
51 lines
1.3 KiB
C
/*
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* Copyright (C) 2009 Lemote Inc.
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* Author: Wu Zhangjin, wuzhangjin@gmail.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/module.h>
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#include <asm/bootinfo.h>
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#include <loongson.h>
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/* raw */
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unsigned long loongson_uart_base[MAX_UARTS] = {};
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/* ioremapped */
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unsigned long _loongson_uart_base[MAX_UARTS] = {};
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EXPORT_SYMBOL(loongson_uart_base);
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EXPORT_SYMBOL(_loongson_uart_base);
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void prom_init_loongson_uart_base(void)
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{
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switch (mips_machtype) {
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case MACH_LOONGSON_GENERIC:
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/* The CPU provided serial port (CPU) */
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loongson_uart_base[0] = LOONGSON_REG_BASE + 0x1e0;
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break;
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case MACH_LEMOTE_FL2E:
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loongson_uart_base[0] = LOONGSON_PCIIO_BASE + 0x3f8;
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break;
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case MACH_LEMOTE_FL2F:
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case MACH_LEMOTE_LL2F:
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loongson_uart_base[0] = LOONGSON_PCIIO_BASE + 0x2f8;
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break;
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case MACH_LEMOTE_ML2F7:
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case MACH_LEMOTE_YL2F89:
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case MACH_DEXXON_GDIUM2F10:
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case MACH_LEMOTE_NAS:
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default:
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/* The CPU provided serial port (LPC) */
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loongson_uart_base[0] = LOONGSON_LIO1_BASE + 0x3f8;
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break;
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}
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_loongson_uart_base[0] =
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(unsigned long)ioremap_nocache(loongson_uart_base[0], 8);
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}
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