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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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db18b6a64c
Currently the machine hangs during booting while accessing the
BXT_MIPI_PORT_CTRL register during pipe HW state readout. After some
experimentation I found that the hang is caused by the DSI PLL being
disabled, or it being enabled but with an incorrect divider
configuration. Enabling the PLL got rid of the boot problem, so fix
this by checking the PLL enabled state/configuration before attempting
to read out the HW state.
The DSI_PLL_ENABLE register is in the always-on power well, while the
BXT_DSI_PLL_CTL is in power well 0. This isn't exactly matched by the
transcoder power domain, but what we really need is just a runtime PM
reference, which is provided by any power domain.
Ville also found this dependency specified in BSpec, so I added a
reference to that too.
v2:
- Make sure we hold a power reference while accessing the PLL registers.
v3: (Jani)
- Simplify check in bxt_get_dsi_transcoder_state()
- Add comment explaining why we check for valid dividers in
bxt_dsi_pll_is_enabled()
CC: Shashank Sharma <shashank.sharma@intel.com>
CC: Uma Shankar <uma.shankar@intel.com>
CC: Jani Nikula <jani.nikula@intel.com>
Fixes: c6c794a2fc ("drm/i915/bxt: Initialize MIPI DSI for BXT")
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1458816100-31269-1-git-send-email-imre.deak@intel.com
139 lines
3.7 KiB
C
139 lines
3.7 KiB
C
/*
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* Copyright © 2013 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _INTEL_DSI_H
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#define _INTEL_DSI_H
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#include <drm/drmP.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_mipi_dsi.h>
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#include "intel_drv.h"
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/* Dual Link support */
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#define DSI_DUAL_LINK_NONE 0
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#define DSI_DUAL_LINK_FRONT_BACK 1
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#define DSI_DUAL_LINK_PIXEL_ALT 2
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struct intel_dsi_host;
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struct intel_dsi {
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struct intel_encoder base;
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struct drm_panel *panel;
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struct intel_dsi_host *dsi_hosts[I915_MAX_PORTS];
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/* GPIO Desc for CRC based Panel control */
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struct gpio_desc *gpio_panel;
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struct intel_connector *attached_connector;
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/* bit mask of ports being driven */
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u16 ports;
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/* if true, use HS mode, otherwise LP */
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bool hs;
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/* virtual channel */
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int channel;
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/* Video mode or command mode */
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u16 operation_mode;
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/* number of DSI lanes */
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unsigned int lane_count;
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/*
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* video mode pixel format
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*
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* XXX: consolidate on .format in struct mipi_dsi_device.
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*/
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enum mipi_dsi_pixel_format pixel_format;
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/* video mode format for MIPI_VIDEO_MODE_FORMAT register */
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u32 video_mode_format;
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/* eot for MIPI_EOT_DISABLE register */
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u8 eotp_pkt;
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u8 clock_stop;
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u8 escape_clk_div;
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u8 dual_link;
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u8 pixel_overlap;
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u32 port_bits;
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u32 bw_timer;
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u32 dphy_reg;
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u32 video_frmt_cfg_bits;
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u16 lp_byte_clk;
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/* timeouts in byte clocks */
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u16 lp_rx_timeout;
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u16 turn_arnd_val;
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u16 rst_timer_val;
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u16 hs_to_lp_count;
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u16 clk_lp_to_hs_count;
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u16 clk_hs_to_lp_count;
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u16 init_count;
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u32 pclk;
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u16 burst_mode_ratio;
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/* all delays in ms */
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u16 backlight_off_delay;
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u16 backlight_on_delay;
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u16 panel_on_delay;
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u16 panel_off_delay;
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u16 panel_pwr_cycle_delay;
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};
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struct intel_dsi_host {
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struct mipi_dsi_host base;
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struct intel_dsi *intel_dsi;
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enum port port;
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/* our little hack */
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struct mipi_dsi_device *device;
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};
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static inline struct intel_dsi_host *to_intel_dsi_host(struct mipi_dsi_host *h)
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{
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return container_of(h, struct intel_dsi_host, base);
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}
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#define for_each_dsi_port(__port, __ports_mask) for_each_port_masked(__port, __ports_mask)
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static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
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{
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return container_of(encoder, struct intel_dsi, base.base);
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}
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bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv);
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extern void intel_enable_dsi_pll(struct intel_encoder *encoder);
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extern void intel_disable_dsi_pll(struct intel_encoder *encoder);
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extern u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp);
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extern void intel_dsi_reset_clocks(struct intel_encoder *encoder,
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enum port port);
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struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id);
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#endif /* _INTEL_DSI_H */
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