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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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91c703e038
Calling __cpuc_coherent_user_range to invalidate the icache on a PIPT icache machine has some pointless overhead, as it starts by cleaning the dcache to the PoU, while we're guaranteed to have already cleaned it to the PoC. As KVM is the only user of such a feature, let's implement some ad-hoc cache flushing in kvm_mmu.h. Should it become useful to other subsystems, it can be moved to a more global location. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
129 lines
4.6 KiB
C
129 lines
4.6 KiB
C
/*
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* Copyright (C) 2015 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ARM_KVM_HYP_H__
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#define __ARM_KVM_HYP_H__
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#include <linux/compiler.h>
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#include <linux/kvm_host.h>
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#include <asm/cp15.h>
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#include <asm/vfp.h>
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#define __hyp_text __section(.hyp.text) notrace
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#define __ACCESS_VFP(CRn) \
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"mrc", "mcr", __stringify(p10, 7, %0, CRn, cr0, 0), u32
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#define write_special(v, r) \
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asm volatile("msr " __stringify(r) ", %0" : : "r" (v))
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#define read_special(r) ({ \
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u32 __val; \
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asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
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__val; \
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})
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#define TTBR0 __ACCESS_CP15_64(0, c2)
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#define TTBR1 __ACCESS_CP15_64(1, c2)
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#define VTTBR __ACCESS_CP15_64(6, c2)
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#define PAR __ACCESS_CP15_64(0, c7)
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#define CNTV_CVAL __ACCESS_CP15_64(3, c14)
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#define CNTVOFF __ACCESS_CP15_64(4, c14)
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#define MIDR __ACCESS_CP15(c0, 0, c0, 0)
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#define CSSELR __ACCESS_CP15(c0, 2, c0, 0)
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#define VPIDR __ACCESS_CP15(c0, 4, c0, 0)
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#define VMPIDR __ACCESS_CP15(c0, 4, c0, 5)
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#define SCTLR __ACCESS_CP15(c1, 0, c0, 0)
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#define CPACR __ACCESS_CP15(c1, 0, c0, 2)
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#define HCR __ACCESS_CP15(c1, 4, c1, 0)
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#define HDCR __ACCESS_CP15(c1, 4, c1, 1)
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#define HCPTR __ACCESS_CP15(c1, 4, c1, 2)
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#define HSTR __ACCESS_CP15(c1, 4, c1, 3)
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#define TTBCR __ACCESS_CP15(c2, 0, c0, 2)
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#define HTCR __ACCESS_CP15(c2, 4, c0, 2)
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#define VTCR __ACCESS_CP15(c2, 4, c1, 2)
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#define DACR __ACCESS_CP15(c3, 0, c0, 0)
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#define DFSR __ACCESS_CP15(c5, 0, c0, 0)
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#define IFSR __ACCESS_CP15(c5, 0, c0, 1)
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#define ADFSR __ACCESS_CP15(c5, 0, c1, 0)
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#define AIFSR __ACCESS_CP15(c5, 0, c1, 1)
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#define HSR __ACCESS_CP15(c5, 4, c2, 0)
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#define DFAR __ACCESS_CP15(c6, 0, c0, 0)
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#define IFAR __ACCESS_CP15(c6, 0, c0, 2)
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#define HDFAR __ACCESS_CP15(c6, 4, c0, 0)
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#define HIFAR __ACCESS_CP15(c6, 4, c0, 2)
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#define HPFAR __ACCESS_CP15(c6, 4, c0, 4)
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#define ICIALLUIS __ACCESS_CP15(c7, 0, c1, 0)
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#define BPIALLIS __ACCESS_CP15(c7, 0, c1, 6)
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#define ICIMVAU __ACCESS_CP15(c7, 0, c5, 1)
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#define ATS1CPR __ACCESS_CP15(c7, 0, c8, 0)
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#define TLBIALLIS __ACCESS_CP15(c8, 0, c3, 0)
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#define TLBIALL __ACCESS_CP15(c8, 0, c7, 0)
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#define TLBIALLNSNHIS __ACCESS_CP15(c8, 4, c3, 4)
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#define PRRR __ACCESS_CP15(c10, 0, c2, 0)
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#define NMRR __ACCESS_CP15(c10, 0, c2, 1)
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#define AMAIR0 __ACCESS_CP15(c10, 0, c3, 0)
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#define AMAIR1 __ACCESS_CP15(c10, 0, c3, 1)
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#define VBAR __ACCESS_CP15(c12, 0, c0, 0)
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#define CID __ACCESS_CP15(c13, 0, c0, 1)
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#define TID_URW __ACCESS_CP15(c13, 0, c0, 2)
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#define TID_URO __ACCESS_CP15(c13, 0, c0, 3)
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#define TID_PRIV __ACCESS_CP15(c13, 0, c0, 4)
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#define HTPIDR __ACCESS_CP15(c13, 4, c0, 2)
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#define CNTKCTL __ACCESS_CP15(c14, 0, c1, 0)
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#define CNTV_CTL __ACCESS_CP15(c14, 0, c3, 1)
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#define CNTHCTL __ACCESS_CP15(c14, 4, c1, 0)
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#define VFP_FPEXC __ACCESS_VFP(FPEXC)
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/* AArch64 compatibility macros, only for the timer so far */
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#define read_sysreg_el0(r) read_sysreg(r##_el0)
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#define write_sysreg_el0(v, r) write_sysreg(v, r##_el0)
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#define cntv_ctl_el0 CNTV_CTL
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#define cntv_cval_el0 CNTV_CVAL
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#define cntvoff_el2 CNTVOFF
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#define cnthctl_el2 CNTHCTL
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void __timer_enable_traps(struct kvm_vcpu *vcpu);
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void __timer_disable_traps(struct kvm_vcpu *vcpu);
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void __vgic_v2_save_state(struct kvm_vcpu *vcpu);
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void __vgic_v2_restore_state(struct kvm_vcpu *vcpu);
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void __sysreg_save_state(struct kvm_cpu_context *ctxt);
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void __sysreg_restore_state(struct kvm_cpu_context *ctxt);
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void __vgic_v3_save_state(struct kvm_vcpu *vcpu);
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void __vgic_v3_restore_state(struct kvm_vcpu *vcpu);
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asmlinkage void __vfp_save_state(struct vfp_hard_struct *vfp);
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asmlinkage void __vfp_restore_state(struct vfp_hard_struct *vfp);
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static inline bool __vfp_enabled(void)
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{
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return !(read_sysreg(HCPTR) & (HCPTR_TCP(11) | HCPTR_TCP(10)));
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}
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void __hyp_text __banked_save_state(struct kvm_cpu_context *ctxt);
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void __hyp_text __banked_restore_state(struct kvm_cpu_context *ctxt);
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asmlinkage int __guest_enter(struct kvm_vcpu *vcpu,
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struct kvm_cpu_context *host);
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asmlinkage int __hyp_do_panic(const char *, int, u32);
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#endif /* __ARM_KVM_HYP_H__ */
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