mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 06:50:52 +07:00
07afb8db73
Add a clock driver for the Stratix10 SoC. The driver is similar to the Cyclone5/Arria10 platforms, with the exception that this driver only uses one single clock binding. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
||
|---|---|---|
| .. | ||
| clk-gate-a10.c | ||
| clk-gate-s10.c | ||
| clk-gate.c | ||
| clk-periph-a10.c | ||
| clk-periph-s10.c | ||
| clk-periph.c | ||
| clk-pll-a10.c | ||
| clk-pll-s10.c | ||
| clk-pll.c | ||
| clk-s10.c | ||
| clk.c | ||
| clk.h | ||
| Makefile | ||
| stratix10-clk.h | ||