mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 00:30:53 +07:00
5a3aa2a8fa
Add a reference platform driver for PCI RC IP Protoyping Kits based on the ARC SDP. [bhelgaas: changelog, split patch up, MAINTAINERS update] Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
139 lines
3.1 KiB
C
139 lines
3.1 KiB
C
/*
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* PCIe RC driver for Synopsys DesignWare Core
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*
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* Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
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*
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* Authors: Joao Pinto <jpinto@synopsys.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/gpio.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_gpio.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/resource.h>
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#include <linux/signal.h>
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#include <linux/types.h>
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#include "pcie-designware.h"
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struct dw_plat_pcie {
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void __iomem *mem_base;
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struct pcie_port pp;
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};
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static irqreturn_t dw_plat_pcie_msi_irq_handler(int irq, void *arg)
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{
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struct pcie_port *pp = arg;
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return dw_handle_msi_irq(pp);
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}
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static void dw_plat_pcie_host_init(struct pcie_port *pp)
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{
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dw_pcie_setup_rc(pp);
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dw_pcie_wait_for_link(pp);
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if (IS_ENABLED(CONFIG_PCI_MSI))
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dw_pcie_msi_init(pp);
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}
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static struct pcie_host_ops dw_plat_pcie_host_ops = {
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.host_init = dw_plat_pcie_host_init,
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};
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static int dw_plat_add_pcie_port(struct pcie_port *pp,
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struct platform_device *pdev)
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{
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int ret;
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pp->irq = platform_get_irq(pdev, 1);
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if (pp->irq < 0)
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return pp->irq;
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if (IS_ENABLED(CONFIG_PCI_MSI)) {
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pp->msi_irq = platform_get_irq(pdev, 0);
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if (pp->msi_irq < 0)
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return pp->msi_irq;
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ret = devm_request_irq(&pdev->dev, pp->msi_irq,
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dw_plat_pcie_msi_irq_handler,
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IRQF_SHARED, "dw-plat-pcie-msi", pp);
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if (ret) {
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dev_err(&pdev->dev, "failed to request MSI IRQ\n");
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return ret;
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}
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}
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pp->root_bus_nr = -1;
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pp->ops = &dw_plat_pcie_host_ops;
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ret = dw_pcie_host_init(pp);
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if (ret) {
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dev_err(&pdev->dev, "failed to initialize host\n");
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return ret;
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}
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return 0;
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}
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static int dw_plat_pcie_probe(struct platform_device *pdev)
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{
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struct dw_plat_pcie *dw_plat_pcie;
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struct pcie_port *pp;
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struct resource *res; /* Resource from DT */
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int ret;
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dw_plat_pcie = devm_kzalloc(&pdev->dev, sizeof(*dw_plat_pcie),
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GFP_KERNEL);
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if (!dw_plat_pcie)
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return -ENOMEM;
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pp = &dw_plat_pcie->pp;
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pp->dev = &pdev->dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENODEV;
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dw_plat_pcie->mem_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(dw_plat_pcie->mem_base))
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return PTR_ERR(dw_plat_pcie->mem_base);
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pp->dbi_base = dw_plat_pcie->mem_base;
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ret = dw_plat_add_pcie_port(pp, pdev);
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if (ret < 0)
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return ret;
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platform_set_drvdata(pdev, dw_plat_pcie);
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return 0;
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}
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static const struct of_device_id dw_plat_pcie_of_match[] = {
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{ .compatible = "snps,dw-pcie", },
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{},
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};
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MODULE_DEVICE_TABLE(of, dw_plat_pcie_of_match);
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static struct platform_driver dw_plat_pcie_driver = {
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.driver = {
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.name = "dw-pcie",
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.of_match_table = dw_plat_pcie_of_match,
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},
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.probe = dw_plat_pcie_probe,
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};
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module_platform_driver(dw_plat_pcie_driver);
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MODULE_AUTHOR("Joao Pinto <Joao.Pinto@synopsys.com>");
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MODULE_DESCRIPTION("Synopsys PCIe host controller glue platform driver");
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MODULE_LICENSE("GPL v2");
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