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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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3c9b9accad
The sh code is mostly equivalent to the generic one, minus various bugfixes and two arch overrides that this patch adds to pgtable.h. Link: http://lkml.kernel.org/r/20190625143715.1689-7-hch@lst.de Signed-off-by: Christoph Hellwig <hch@lst.de> Cc: Andrey Konovalov <andreyknvl@google.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: David Miller <davem@davemloft.net> Cc: James Hogan <jhogan@kernel.org> Cc: Jason Gunthorpe <jgg@mellanox.com> Cc: Khalid Aziz <khalid.aziz@oracle.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Paul Burton <paul.burton@mips.com> Cc: Paul Mackerras <paulus@samba.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Rich Felker <dalias@libc.org> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
75 lines
2.6 KiB
Makefile
75 lines
2.6 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0
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#
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# Makefile for the Linux SuperH-specific parts of the memory manager.
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#
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obj-y := alignment.o cache.o init.o consistent.o mmap.o
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cacheops-$(CONFIG_CPU_J2) := cache-j2.o
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cacheops-$(CONFIG_CPU_SUBTYPE_SH7619) := cache-sh2.o
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cacheops-$(CONFIG_CPU_SH2A) := cache-sh2a.o
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cacheops-$(CONFIG_CPU_SH3) := cache-sh3.o
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cacheops-$(CONFIG_CPU_SH4) := cache-sh4.o flush-sh4.o
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cacheops-$(CONFIG_CPU_SH5) := cache-sh5.o flush-sh4.o
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cacheops-$(CONFIG_SH7705_CACHE_32KB) += cache-sh7705.o
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cacheops-$(CONFIG_CPU_SHX3) += cache-shx3.o
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obj-y += $(cacheops-y)
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mmu-y := nommu.o extable_32.o
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mmu-$(CONFIG_MMU) := extable_$(BITS).o fault.o ioremap.o kmap.o \
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pgtable.o tlbex_$(BITS).o tlbflush_$(BITS).o
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obj-y += $(mmu-y)
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debugfs-y := asids-debugfs.o
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ifndef CONFIG_CACHE_OFF
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debugfs-$(CONFIG_CPU_SH4) += cache-debugfs.o
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endif
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ifdef CONFIG_MMU
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debugfs-$(CONFIG_CPU_SH4) += tlb-debugfs.o
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tlb-$(CONFIG_CPU_SH3) := tlb-sh3.o
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tlb-$(CONFIG_CPU_SH4) := tlb-sh4.o tlb-urb.o
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tlb-$(CONFIG_CPU_SH5) := tlb-sh5.o
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tlb-$(CONFIG_CPU_HAS_PTEAEX) := tlb-pteaex.o tlb-urb.o
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obj-y += $(tlb-y)
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endif
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obj-$(CONFIG_DEBUG_FS) += $(debugfs-y)
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obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
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obj-$(CONFIG_PMB) += pmb.o
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obj-$(CONFIG_NUMA) += numa.o
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obj-$(CONFIG_IOREMAP_FIXED) += ioremap_fixed.o
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obj-$(CONFIG_UNCACHED_MAPPING) += uncached.o
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obj-$(CONFIG_HAVE_SRAM_POOL) += sram.o
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GCOV_PROFILE_pmb.o := n
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# Special flags for tlbex_64.o. This puts restrictions on the number of
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# caller-save registers that the compiler can target when building this file.
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# This is required because the code is called from a context in entry.S where
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# very few registers have been saved in the exception handler (for speed
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# reasons).
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# The caller save registers that have been saved and which can be used are
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# r2,r3,r4,r5 : argument passing
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# r15, r18 : SP and LINK
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# tr0-4 : allow all caller-save TR's. The compiler seems to be able to make
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# use of them, so it's probably beneficial to performance to save them
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# and have them available for it.
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#
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# The resources not listed below are callee save, i.e. the compiler is free to
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# use any of them and will spill them to the stack itself.
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CFLAGS_tlbex_64.o += -ffixed-r7 \
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-ffixed-r8 -ffixed-r9 -ffixed-r10 -ffixed-r11 -ffixed-r12 \
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-ffixed-r13 -ffixed-r14 -ffixed-r16 -ffixed-r17 -ffixed-r19 \
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-ffixed-r20 -ffixed-r21 -ffixed-r22 -ffixed-r23 \
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-ffixed-r24 -ffixed-r25 -ffixed-r26 -ffixed-r27 \
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-ffixed-r36 -ffixed-r37 -ffixed-r38 -ffixed-r39 -ffixed-r40 \
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-ffixed-r41 -ffixed-r42 -ffixed-r43 \
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-ffixed-r60 -ffixed-r61 -ffixed-r62 \
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-fomit-frame-pointer
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ccflags-y := -Werror
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