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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ff4a7481c3
Update license to use SPDX-License-Identifier instead of verbose license
text.
As original license mentioned, it is GPL-2.0 in SPDX.
Then, MODULE_LICENSE() should be "GPL v2" instead of "GPL".
See ${LINUX}/include/linux/module.h
"GPL" [GNU Public License v2 or later]
"GPL v2" [GNU Public License v2]
Link: http://lkml.kernel.org/r/87h8fsct0a.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Cc: Rich Felker <dalias@libc.org>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
44 lines
1.6 KiB
C
44 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Low-Level PCI Support for SH7780 targets
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*
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* Dustin McIntire (dustin@sensoria.com) (c) 2001
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* Paul Mundt (lethal@linux-sh.org) (c) 2003
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*/
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#ifndef _PCI_SH7780_H_
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#define _PCI_SH7780_H_
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/* SH7780 Control Registers */
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#define PCIECR 0xFE000008
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#define PCIECR_ENBL 0x01
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/* SH7780 Specific Values */
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#define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
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#define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */
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#define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
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/* SH7780 PCI Config Registers */
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#define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
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#define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
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#define SH7780_PCIAIR 0x11C /* Error Address Register */
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#define SH7780_PCICIR 0x120 /* Error Command/Data Register */
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#define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */
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#define SH7780_PCIAINTM 0x134 /* Arbiter Int. Mask Register */
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#define SH7780_PCIBMIR 0x138 /* Error Bus Master Register */
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#define SH7780_PCIPAR 0x1C0 /* PIO Address Register */
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#define SH7780_PCIPINT 0x1CC /* Power Mgmnt Int. Register */
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#define SH7780_PCIPINTM 0x1D0 /* Power Mgmnt Mask Register */
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#define SH7780_PCIMBR(x) (0x1E0 + ((x) * 8))
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#define SH7780_PCIMBMR(x) (0x1E4 + ((x) * 8))
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#define SH7780_PCIIOBR 0x1F8
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#define SH7780_PCIIOBMR 0x1FC
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#define SH7780_PCICSCR0 0x210 /* Cache Snoop1 Cnt. Register */
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#define SH7780_PCICSCR1 0x214 /* Cache Snoop2 Cnt. Register */
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#define SH7780_PCICSAR0 0x218 /* Cache Snoop1 Addr. Register */
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#define SH7780_PCICSAR1 0x21C /* Cache Snoop2 Addr. Register */
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#endif /* _PCI_SH7780_H_ */
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