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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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364 lines
9.8 KiB
C
364 lines
9.8 KiB
C
/*
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* Copyright 2001 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ahennessy@mvista.com
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*
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* Copyright (C) 2000-2001 Toshiba Corporation
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* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
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*
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* Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c
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*
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* Define the pci_ops for JMR3927.
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*
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* Much of the code is derived from the original DDB5074 port by
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* Geert Uytterhoeven <geert@sonycom.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <asm/addrspace.h>
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#include <asm/jmr3927/jmr3927.h>
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#include <asm/debug.h>
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static inline int mkaddr(unsigned char bus, unsigned char dev_fn,
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unsigned char where)
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{
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if (bus == 0 && dev_fn >= PCI_DEVFN(TX3927_PCIC_MAX_DEVNU, 0))
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return PCIBIOS_DEVICE_NOT_FOUND;
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tx3927_pcicptr->ica = ((bus & 0xff) << 0x10) |
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((dev_fn & 0xff) << 0x08) |
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(where & 0xfc);
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/* clear M_ABORT and Disable M_ABORT Int. */
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tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
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tx3927_pcicptr->pcistatim &= ~PCI_STATUS_REC_MASTER_ABORT;
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return PCIBIOS_SUCCESSFUL;
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}
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static inline int check_abort(void)
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{
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if (tx3927_pcicptr->pcistat & PCI_STATUS_REC_MASTER_ABORT)
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tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
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tx3927_pcicptr->pcistatim |= PCI_STATUS_REC_MASTER_ABORT;
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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}
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static int jmr3927_pci_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 * val)
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{
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int ret;
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ret = mkaddr(bus->number, devfn, where);
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if (ret)
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return ret;
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switch (size) {
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case 1:
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*val = *(volatile u8 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3));
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break;
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case 2:
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*val = le16_to_cpu(*(volatile u16 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3)));
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break;
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case 4:
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*val = le32_to_cpu(tx3927_pcicptr->icd);
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break;
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}
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return check_abort();
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}
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static int jmr3927_pci_write_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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int ret;
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ret = mkaddr(bus->number, devfn, where);
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if (ret)
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return ret;
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switch (size) {
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case 1:
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*(volatile u8 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3)) = val;
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break;
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case 2:
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*(volatile u16 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 2)) =
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cpu_to_le16(val);
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break;
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case 4:
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tx3927_pcicptr->icd = cpu_to_le32(val);
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}
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if (tx3927_pcicptr->pcistat & PCI_STATUS_REC_MASTER_ABORT)
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tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
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tx3927_pcicptr->pcistatim |= PCI_STATUS_REC_MASTER_ABORT;
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return PCIBIOS_DEVICE_NOT_FOUND;
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return check_abort();
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}
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struct pci_ops jmr3927_pci_ops = {
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jmr3927_pci_read_config,
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jmr3927_pci_write_config,
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};
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#ifndef JMR3927_INIT_INDIRECT_PCI
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inline unsigned long tc_readl(volatile __u32 * addr)
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{
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return readl(addr);
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}
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inline void tc_writel(unsigned long data, volatile __u32 * addr)
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{
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writel(data, addr);
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}
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#else
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unsigned long tc_readl(volatile __u32 * addr)
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{
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unsigned long val;
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*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
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(unsigned long) CPHYSADDR(addr);
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*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
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(PCI_IPCIBE_ICMD_MEMREAD << PCI_IPCIBE_ICMD_SHIFT) |
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PCI_IPCIBE_IBE_LONG;
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while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
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val =
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le32_to_cpu(*(volatile u32 *) (unsigned long) & tx3927_pcicptr->
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ipcidata);
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/* clear by setting */
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tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
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return val;
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}
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void tc_writel(unsigned long data, volatile __u32 * addr)
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{
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*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcidata =
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cpu_to_le32(data);
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*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
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(unsigned long) CPHYSADDR(addr);
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*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
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(PCI_IPCIBE_ICMD_MEMWRITE << PCI_IPCIBE_ICMD_SHIFT) |
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PCI_IPCIBE_IBE_LONG;
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while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
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/* clear by setting */
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tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
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}
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unsigned char tx_ioinb(unsigned char *addr)
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{
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unsigned long val;
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__u32 ioaddr;
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int offset;
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int byte;
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ioaddr = (unsigned long) addr;
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offset = ioaddr & 0x3;
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byte = 0xf & ~(8 >> offset);
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*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
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(unsigned long) ioaddr;
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*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
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(PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | byte;
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while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
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val =
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le32_to_cpu(*(volatile u32 *) (unsigned long) & tx3927_pcicptr->
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ipcidata);
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val = val & 0xff;
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/* clear by setting */
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tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
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return val;
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}
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void tx_iooutb(unsigned long data, unsigned char *addr)
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{
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__u32 ioaddr;
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int offset;
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int byte;
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data = data | (data << 8) | (data << 16) | (data << 24);
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ioaddr = (unsigned long) addr;
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offset = ioaddr & 0x3;
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byte = 0xf & ~(8 >> offset);
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*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcidata = data;
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*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
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(unsigned long) ioaddr;
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*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
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(PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | byte;
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while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
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/* clear by setting */
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tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
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}
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unsigned short tx_ioinw(unsigned short *addr)
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{
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unsigned long val;
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__u32 ioaddr;
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int offset;
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int byte;
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ioaddr = (unsigned long) addr;
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offset = ioaddr & 0x2;
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byte = 3 << offset;
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*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
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(unsigned long) ioaddr;
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*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
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(PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) | byte;
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while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
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val =
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le32_to_cpu(*(volatile u32 *) (unsigned long) & tx3927_pcicptr->
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ipcidata);
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val = val & 0xffff;
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/* clear by setting */
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tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
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return val;
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}
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void tx_iooutw(unsigned long data, unsigned short *addr)
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{
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__u32 ioaddr;
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int offset;
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int byte;
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data = data | (data << 16);
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ioaddr = (unsigned long) addr;
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offset = ioaddr & 0x2;
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byte = 3 << offset;
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*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcidata = data;
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*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
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(unsigned long) ioaddr;
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*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
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(PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) | byte;
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while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
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/* clear by setting */
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tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
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}
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unsigned long tx_ioinl(unsigned int *addr)
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{
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unsigned long val;
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__u32 ioaddr;
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ioaddr = (unsigned long) addr;
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*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
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(unsigned long) ioaddr;
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*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
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(PCI_IPCIBE_ICMD_IOREAD << PCI_IPCIBE_ICMD_SHIFT) |
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PCI_IPCIBE_IBE_LONG;
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while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
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val =
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le32_to_cpu(*(volatile u32 *) (unsigned long) & tx3927_pcicptr->
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ipcidata);
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/* clear by setting */
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tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
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return val;
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}
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void tx_iooutl(unsigned long data, unsigned int *addr)
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{
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__u32 ioaddr;
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ioaddr = (unsigned long) addr;
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*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcidata =
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cpu_to_le32(data);
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*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipciaddr =
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(unsigned long) ioaddr;
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*(volatile u32 *) (unsigned long) & tx3927_pcicptr->ipcibe =
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(PCI_IPCIBE_ICMD_IOWRITE << PCI_IPCIBE_ICMD_SHIFT) |
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PCI_IPCIBE_IBE_LONG;
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while (!(tx3927_pcicptr->istat & PCI_ISTAT_IDICC));
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/* clear by setting */
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tx3927_pcicptr->istat |= PCI_ISTAT_IDICC;
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}
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void tx_insbyte(unsigned char *addr, void *buffer, unsigned int count)
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{
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unsigned char *ptr = (unsigned char *) buffer;
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while (count--) {
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*ptr++ = tx_ioinb(addr);
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}
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}
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void tx_insword(unsigned short *addr, void *buffer, unsigned int count)
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{
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unsigned short *ptr = (unsigned short *) buffer;
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while (count--) {
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*ptr++ = tx_ioinw(addr);
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}
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}
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void tx_inslong(unsigned int *addr, void *buffer, unsigned int count)
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{
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unsigned long *ptr = (unsigned long *) buffer;
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while (count--) {
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*ptr++ = tx_ioinl(addr);
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}
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}
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void tx_outsbyte(unsigned char *addr, void *buffer, unsigned int count)
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{
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unsigned char *ptr = (unsigned char *) buffer;
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while (count--) {
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tx_iooutb(*ptr++, addr);
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}
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}
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void tx_outsword(unsigned short *addr, void *buffer, unsigned int count)
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{
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unsigned short *ptr = (unsigned short *) buffer;
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while (count--) {
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tx_iooutw(*ptr++, addr);
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}
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}
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void tx_outslong(unsigned int *addr, void *buffer, unsigned int count)
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{
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unsigned long *ptr = (unsigned long *) buffer;
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while (count--) {
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tx_iooutl(*ptr++, addr);
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}
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}
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#endif
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