mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-19 01:57:15 +07:00
b0d8003ef4
Mostly complete rewrite of the FRV atomic implementation, instead of
using assembly files, use inline assembler.
The out-of-line CONFIG option makes a bit of a mess of things, but a
little CPP trickery gets that done too.
FRV already had the atomic logic ops but under a non standard name,
the reimplementation provides the generic names and provides the
intermediate form required for the bitops implementation.
The slightly inconsistent __atomic32_fetch_##op naming is because
__atomic_fetch_##op conlicts with GCC builtin functions.
The 64bit atomic ops use the inline assembly %Ln construct to access
the low word register (r+1), afaik this construct was not previously
used in the kernel and is completely undocumented, but I found it in
the FRV GCC code and it seems to work.
FRV had a non-standard definition of atomic_{clear,set}_mask() which
would work types other than atomic_t, the one user relying on that
(arch/frv/kernel/dma.c) got converted to use the new intermediate
form.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
63 lines
1.7 KiB
ArmAsm
63 lines
1.7 KiB
ArmAsm
/* atomic-ops.S: kernel atomic operations
|
|
*
|
|
* For an explanation of how atomic ops work in this arch, see:
|
|
* Documentation/frv/atomic-ops.txt
|
|
*
|
|
* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
|
|
* Written by David Howells (dhowells@redhat.com)
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License
|
|
* as published by the Free Software Foundation; either version
|
|
* 2 of the License, or (at your option) any later version.
|
|
*/
|
|
|
|
#include <asm/spr-regs.h>
|
|
|
|
.text
|
|
.balign 4
|
|
|
|
###############################################################################
|
|
#
|
|
# uint32_t __xchg_32(uint32_t i, uint32_t *v)
|
|
#
|
|
###############################################################################
|
|
.globl __xchg_32
|
|
.type __xchg_32,@function
|
|
__xchg_32:
|
|
or.p gr8,gr8,gr10
|
|
0:
|
|
orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
|
|
ckeq icc3,cc7
|
|
ld.p @(gr9,gr0),gr8 /* LD.P/ORCR must be atomic */
|
|
orcr cc7,cc7,cc3 /* set CC3 to true */
|
|
cst.p gr10,@(gr9,gr0) ,cc3,#1
|
|
corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
|
|
beq icc3,#0,0b
|
|
bralr
|
|
|
|
.size __xchg_32, .-__xchg_32
|
|
|
|
###############################################################################
|
|
#
|
|
# uint32_t __cmpxchg_32(uint32_t *v, uint32_t test, uint32_t new)
|
|
#
|
|
###############################################################################
|
|
.globl __cmpxchg_32
|
|
.type __cmpxchg_32,@function
|
|
__cmpxchg_32:
|
|
or.p gr8,gr8,gr11
|
|
0:
|
|
orcc gr0,gr0,gr0,icc3
|
|
ckeq icc3,cc7
|
|
ld.p @(gr11,gr0),gr8
|
|
orcr cc7,cc7,cc3
|
|
subcc gr8,gr9,gr7,icc0
|
|
bnelr icc0,#0
|
|
cst.p gr10,@(gr11,gr0) ,cc3,#1
|
|
corcc gr29,gr29,gr0 ,cc3,#1
|
|
beq icc3,#0,0b
|
|
bralr
|
|
|
|
.size __cmpxchg_32, .-__cmpxchg_32
|