mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 01:45:23 +07:00
baba6e572b
A few advantages: - Prepares us for the planned split of display uncore from GT uncore - Improves our engine-centric view of the world in the engine code and allows us to avoid jumping back to dev_priv. - Allows us to wrap accesses to engine register in nice macros that automatically pick the right mmio base. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190325214940.23632-10-daniele.ceraolospurio@intel.com
335 lines
9.1 KiB
C
335 lines
9.1 KiB
C
/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "i915_drv.h"
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#include "i915_reset.h"
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struct hangcheck {
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u64 acthd;
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u32 seqno;
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enum intel_engine_hangcheck_action action;
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unsigned long action_timestamp;
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int deadlock;
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struct intel_instdone instdone;
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bool wedged:1;
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bool stalled:1;
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};
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static bool instdone_unchanged(u32 current_instdone, u32 *old_instdone)
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{
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u32 tmp = current_instdone | *old_instdone;
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bool unchanged;
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unchanged = tmp == *old_instdone;
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*old_instdone |= tmp;
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return unchanged;
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}
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static bool subunits_stuck(struct intel_engine_cs *engine)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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struct intel_instdone instdone;
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struct intel_instdone *accu_instdone = &engine->hangcheck.instdone;
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bool stuck;
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int slice;
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int subslice;
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if (engine->id != RCS0)
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return true;
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intel_engine_get_instdone(engine, &instdone);
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/* There might be unstable subunit states even when
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* actual head is not moving. Filter out the unstable ones by
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* accumulating the undone -> done transitions and only
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* consider those as progress.
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*/
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stuck = instdone_unchanged(instdone.instdone,
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&accu_instdone->instdone);
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stuck &= instdone_unchanged(instdone.slice_common,
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&accu_instdone->slice_common);
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for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
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stuck &= instdone_unchanged(instdone.sampler[slice][subslice],
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&accu_instdone->sampler[slice][subslice]);
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stuck &= instdone_unchanged(instdone.row[slice][subslice],
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&accu_instdone->row[slice][subslice]);
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}
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return stuck;
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}
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static enum intel_engine_hangcheck_action
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head_stuck(struct intel_engine_cs *engine, u64 acthd)
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{
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if (acthd != engine->hangcheck.acthd) {
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/* Clear subunit states on head movement */
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memset(&engine->hangcheck.instdone, 0,
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sizeof(engine->hangcheck.instdone));
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return ENGINE_ACTIVE_HEAD;
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}
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if (!subunits_stuck(engine))
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return ENGINE_ACTIVE_SUBUNITS;
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return ENGINE_DEAD;
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}
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static enum intel_engine_hangcheck_action
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engine_stuck(struct intel_engine_cs *engine, u64 acthd)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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enum intel_engine_hangcheck_action ha;
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u32 tmp;
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ha = head_stuck(engine, acthd);
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if (ha != ENGINE_DEAD)
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return ha;
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if (IS_GEN(dev_priv, 2))
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return ENGINE_DEAD;
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/* Is the chip hanging on a WAIT_FOR_EVENT?
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* If so we can simply poke the RB_WAIT bit
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* and break the hang. This should work on
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* all but the second generation chipsets.
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*/
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tmp = ENGINE_READ(engine, RING_CTL);
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if (tmp & RING_WAIT) {
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i915_handle_error(dev_priv, engine->mask, 0,
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"stuck wait on %s", engine->name);
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ENGINE_WRITE(engine, RING_CTL, tmp);
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return ENGINE_WAIT_KICK;
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}
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return ENGINE_DEAD;
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}
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static void hangcheck_load_sample(struct intel_engine_cs *engine,
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struct hangcheck *hc)
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{
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hc->acthd = intel_engine_get_active_head(engine);
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hc->seqno = intel_engine_get_hangcheck_seqno(engine);
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}
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static void hangcheck_store_sample(struct intel_engine_cs *engine,
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const struct hangcheck *hc)
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{
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engine->hangcheck.acthd = hc->acthd;
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engine->hangcheck.last_seqno = hc->seqno;
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}
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static enum intel_engine_hangcheck_action
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hangcheck_get_action(struct intel_engine_cs *engine,
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const struct hangcheck *hc)
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{
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if (engine->hangcheck.last_seqno != hc->seqno)
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return ENGINE_ACTIVE_SEQNO;
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if (intel_engine_is_idle(engine))
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return ENGINE_IDLE;
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return engine_stuck(engine, hc->acthd);
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}
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static void hangcheck_accumulate_sample(struct intel_engine_cs *engine,
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struct hangcheck *hc)
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{
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unsigned long timeout = I915_ENGINE_DEAD_TIMEOUT;
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hc->action = hangcheck_get_action(engine, hc);
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/* We always increment the progress
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* if the engine is busy and still processing
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* the same request, so that no single request
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* can run indefinitely (such as a chain of
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* batches). The only time we do not increment
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* the hangcheck score on this ring, if this
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* engine is in a legitimate wait for another
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* engine. In that case the waiting engine is a
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* victim and we want to be sure we catch the
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* right culprit. Then every time we do kick
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* the ring, make it as a progress as the seqno
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* advancement might ensure and if not, it
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* will catch the hanging engine.
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*/
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switch (hc->action) {
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case ENGINE_IDLE:
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case ENGINE_ACTIVE_SEQNO:
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/* Clear head and subunit states on seqno movement */
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hc->acthd = 0;
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memset(&engine->hangcheck.instdone, 0,
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sizeof(engine->hangcheck.instdone));
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/* Intentional fall through */
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case ENGINE_WAIT_KICK:
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case ENGINE_WAIT:
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engine->hangcheck.action_timestamp = jiffies;
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break;
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case ENGINE_ACTIVE_HEAD:
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case ENGINE_ACTIVE_SUBUNITS:
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/*
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* Seqno stuck with still active engine gets leeway,
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* in hopes that it is just a long shader.
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*/
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timeout = I915_SEQNO_DEAD_TIMEOUT;
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break;
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case ENGINE_DEAD:
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break;
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default:
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MISSING_CASE(hc->action);
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}
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hc->stalled = time_after(jiffies,
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engine->hangcheck.action_timestamp + timeout);
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hc->wedged = time_after(jiffies,
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engine->hangcheck.action_timestamp +
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I915_ENGINE_WEDGED_TIMEOUT);
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}
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static void hangcheck_declare_hang(struct drm_i915_private *i915,
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unsigned int hung,
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unsigned int stuck)
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{
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struct intel_engine_cs *engine;
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char msg[80];
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unsigned int tmp;
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int len;
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/* If some rings hung but others were still busy, only
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* blame the hanging rings in the synopsis.
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*/
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if (stuck != hung)
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hung &= ~stuck;
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len = scnprintf(msg, sizeof(msg),
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"%s on ", stuck == hung ? "no progress" : "hang");
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for_each_engine_masked(engine, i915, hung, tmp)
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len += scnprintf(msg + len, sizeof(msg) - len,
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"%s, ", engine->name);
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msg[len-2] = '\0';
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return i915_handle_error(i915, hung, I915_ERROR_CAPTURE, "%s", msg);
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}
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/*
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* This is called when the chip hasn't reported back with completed
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* batchbuffers in a long time. We keep track per ring seqno progress and
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* if there are no progress, hangcheck score for that ring is increased.
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* Further, acthd is inspected to see if the ring is stuck. On stuck case
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* we kick the ring. If we see no progress on three subsequent calls
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* we assume chip is wedged and try to fix it by resetting the chip.
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*/
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static void i915_hangcheck_elapsed(struct work_struct *work)
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{
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struct drm_i915_private *dev_priv =
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container_of(work, typeof(*dev_priv),
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gpu_error.hangcheck_work.work);
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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unsigned int hung = 0, stuck = 0, wedged = 0;
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if (!i915_modparams.enable_hangcheck)
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return;
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if (!READ_ONCE(dev_priv->gt.awake))
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return;
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if (i915_terminally_wedged(dev_priv))
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return;
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/* As enabling the GPU requires fairly extensive mmio access,
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* periodically arm the mmio checker to see if we are triggering
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* any invalid access.
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*/
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intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
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for_each_engine(engine, dev_priv, id) {
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struct hangcheck hc;
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intel_engine_signal_breadcrumbs(engine);
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hangcheck_load_sample(engine, &hc);
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hangcheck_accumulate_sample(engine, &hc);
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hangcheck_store_sample(engine, &hc);
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if (hc.stalled) {
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hung |= engine->mask;
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if (hc.action != ENGINE_DEAD)
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stuck |= engine->mask;
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}
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if (hc.wedged)
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wedged |= engine->mask;
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}
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if (GEM_SHOW_DEBUG() && (hung | stuck)) {
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struct drm_printer p = drm_debug_printer("hangcheck");
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for_each_engine(engine, dev_priv, id) {
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if (intel_engine_is_idle(engine))
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continue;
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intel_engine_dump(engine, &p, "%s\n", engine->name);
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}
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}
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if (wedged) {
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dev_err(dev_priv->drm.dev,
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"GPU recovery timed out,"
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" cancelling all in-flight rendering.\n");
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GEM_TRACE_DUMP();
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i915_gem_set_wedged(dev_priv);
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}
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if (hung)
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hangcheck_declare_hang(dev_priv, hung, stuck);
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/* Reset timer in case GPU hangs without another request being added */
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i915_queue_hangcheck(dev_priv);
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}
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void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
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{
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memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
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engine->hangcheck.action_timestamp = jiffies;
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}
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void intel_hangcheck_init(struct drm_i915_private *i915)
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{
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INIT_DELAYED_WORK(&i915->gpu_error.hangcheck_work,
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i915_hangcheck_elapsed);
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}
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#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
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#include "selftests/intel_hangcheck.c"
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#endif
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