mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 09:26:36 +07:00
b35c0e4543
The call to of_parse_phandle() returns a node pointer with refcount incremented thus it must be explicitly decremented after the last usage. Detected by coccinelle with the following warnings: ./drivers/pci/controller/dwc/pci-layerscape.c:204:1-7: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 198, but without a corresponding object release within this function. Signed-off-by: Wen Yang <wen.yang99@zte.com.cn> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Minghuan Lian <minghuan.Lian@nxp.com> Cc: Mingkai Hu <mingkai.hu@nxp.com> Cc: Roy Zang <roy.zang@nxp.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-pci@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org
343 lines
8.1 KiB
C
343 lines
8.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PCIe host controller driver for Freescale Layerscape SoCs
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*
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* Copyright (C) 2014 Freescale Semiconductor.
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*
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* Author: Minghuan Lian <Minghuan.Lian@freescale.com>
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/resource.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include "pcie-designware.h"
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/* PEX1/2 Misc Ports Status Register */
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#define SCFG_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4)
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#define LTSSM_STATE_SHIFT 20
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#define LTSSM_STATE_MASK 0x3f
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#define LTSSM_PCIE_L0 0x11 /* L0 state */
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/* PEX Internal Configuration Registers */
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#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
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#define PCIE_ABSERR 0x8d0 /* Bridge Slave Error Response Register */
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#define PCIE_ABSERR_SETTING 0x9401 /* Forward error of non-posted request */
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#define PCIE_IATU_NUM 6
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struct ls_pcie_drvdata {
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u32 lut_offset;
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u32 ltssm_shift;
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u32 lut_dbg;
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const struct dw_pcie_host_ops *ops;
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const struct dw_pcie_ops *dw_pcie_ops;
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};
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struct ls_pcie {
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struct dw_pcie *pci;
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void __iomem *lut;
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struct regmap *scfg;
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const struct ls_pcie_drvdata *drvdata;
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int index;
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};
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#define to_ls_pcie(x) dev_get_drvdata((x)->dev)
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static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
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{
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struct dw_pcie *pci = pcie->pci;
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u32 header_type;
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header_type = ioread8(pci->dbi_base + PCI_HEADER_TYPE);
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header_type &= 0x7f;
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return header_type == PCI_HEADER_TYPE_BRIDGE;
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}
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/* Clear multi-function bit */
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static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
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{
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struct dw_pcie *pci = pcie->pci;
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iowrite8(PCI_HEADER_TYPE_BRIDGE, pci->dbi_base + PCI_HEADER_TYPE);
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}
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/* Drop MSG TLP except for Vendor MSG */
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static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
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{
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u32 val;
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struct dw_pcie *pci = pcie->pci;
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val = ioread32(pci->dbi_base + PCIE_STRFMR1);
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val &= 0xDFFFFFFF;
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iowrite32(val, pci->dbi_base + PCIE_STRFMR1);
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}
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static void ls_pcie_disable_outbound_atus(struct ls_pcie *pcie)
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{
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int i;
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for (i = 0; i < PCIE_IATU_NUM; i++)
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dw_pcie_disable_atu(pcie->pci, i, DW_PCIE_REGION_OUTBOUND);
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}
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static int ls1021_pcie_link_up(struct dw_pcie *pci)
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{
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u32 state;
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struct ls_pcie *pcie = to_ls_pcie(pci);
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if (!pcie->scfg)
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return 0;
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regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
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state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
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if (state < LTSSM_PCIE_L0)
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return 0;
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return 1;
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}
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static int ls_pcie_link_up(struct dw_pcie *pci)
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{
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struct ls_pcie *pcie = to_ls_pcie(pci);
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u32 state;
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state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>
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pcie->drvdata->ltssm_shift) &
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LTSSM_STATE_MASK;
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if (state < LTSSM_PCIE_L0)
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return 0;
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return 1;
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}
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/* Forward error response of outbound non-posted requests */
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static void ls_pcie_fix_error_response(struct ls_pcie *pcie)
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{
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struct dw_pcie *pci = pcie->pci;
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iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR);
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}
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static int ls_pcie_host_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct ls_pcie *pcie = to_ls_pcie(pci);
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/*
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* Disable outbound windows configured by the bootloader to avoid
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* one transaction hitting multiple outbound windows.
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* dw_pcie_setup_rc() will reconfigure the outbound windows.
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*/
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ls_pcie_disable_outbound_atus(pcie);
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ls_pcie_fix_error_response(pcie);
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dw_pcie_dbi_ro_wr_en(pci);
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ls_pcie_clear_multifunction(pcie);
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dw_pcie_dbi_ro_wr_dis(pci);
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ls_pcie_drop_msg_tlp(pcie);
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dw_pcie_setup_rc(pp);
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return 0;
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}
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static int ls1021_pcie_host_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct ls_pcie *pcie = to_ls_pcie(pci);
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struct device *dev = pci->dev;
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u32 index[2];
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int ret;
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pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
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"fsl,pcie-scfg");
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if (IS_ERR(pcie->scfg)) {
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ret = PTR_ERR(pcie->scfg);
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dev_err(dev, "No syscfg phandle specified\n");
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pcie->scfg = NULL;
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return ret;
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}
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if (of_property_read_u32_array(dev->of_node,
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"fsl,pcie-scfg", index, 2)) {
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pcie->scfg = NULL;
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return -EINVAL;
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}
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pcie->index = index[1];
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return ls_pcie_host_init(pp);
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}
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static int ls_pcie_msi_host_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct device *dev = pci->dev;
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struct device_node *np = dev->of_node;
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struct device_node *msi_node;
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/*
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* The MSI domain is set by the generic of_msi_configure(). This
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* .msi_host_init() function keeps us from doing the default MSI
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* domain setup in dw_pcie_host_init() and also enforces the
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* requirement that "msi-parent" exists.
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*/
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msi_node = of_parse_phandle(np, "msi-parent", 0);
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if (!msi_node) {
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dev_err(dev, "failed to find msi-parent\n");
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return -EINVAL;
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}
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of_node_put(msi_node);
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return 0;
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}
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static const struct dw_pcie_host_ops ls1021_pcie_host_ops = {
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.host_init = ls1021_pcie_host_init,
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.msi_host_init = ls_pcie_msi_host_init,
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};
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static const struct dw_pcie_host_ops ls_pcie_host_ops = {
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.host_init = ls_pcie_host_init,
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.msi_host_init = ls_pcie_msi_host_init,
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};
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static const struct dw_pcie_ops dw_ls1021_pcie_ops = {
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.link_up = ls1021_pcie_link_up,
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};
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static const struct dw_pcie_ops dw_ls_pcie_ops = {
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.link_up = ls_pcie_link_up,
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};
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static const struct ls_pcie_drvdata ls1021_drvdata = {
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.ops = &ls1021_pcie_host_ops,
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.dw_pcie_ops = &dw_ls1021_pcie_ops,
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};
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static const struct ls_pcie_drvdata ls1043_drvdata = {
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.lut_offset = 0x10000,
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.ltssm_shift = 24,
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.lut_dbg = 0x7fc,
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.ops = &ls_pcie_host_ops,
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.dw_pcie_ops = &dw_ls_pcie_ops,
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};
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static const struct ls_pcie_drvdata ls1046_drvdata = {
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.lut_offset = 0x80000,
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.ltssm_shift = 24,
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.lut_dbg = 0x407fc,
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.ops = &ls_pcie_host_ops,
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.dw_pcie_ops = &dw_ls_pcie_ops,
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};
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static const struct ls_pcie_drvdata ls2080_drvdata = {
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.lut_offset = 0x80000,
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.ltssm_shift = 0,
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.lut_dbg = 0x7fc,
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.ops = &ls_pcie_host_ops,
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.dw_pcie_ops = &dw_ls_pcie_ops,
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};
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static const struct ls_pcie_drvdata ls2088_drvdata = {
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.lut_offset = 0x80000,
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.ltssm_shift = 0,
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.lut_dbg = 0x407fc,
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.ops = &ls_pcie_host_ops,
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.dw_pcie_ops = &dw_ls_pcie_ops,
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};
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static const struct of_device_id ls_pcie_of_match[] = {
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{ .compatible = "fsl,ls1012a-pcie", .data = &ls1046_drvdata },
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{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
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{ .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
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{ .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
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{ .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
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{ .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
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{ .compatible = "fsl,ls2088a-pcie", .data = &ls2088_drvdata },
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{ .compatible = "fsl,ls1088a-pcie", .data = &ls2088_drvdata },
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{ },
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};
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static int __init ls_add_pcie_port(struct ls_pcie *pcie)
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{
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struct dw_pcie *pci = pcie->pci;
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struct pcie_port *pp = &pci->pp;
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struct device *dev = pci->dev;
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int ret;
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pp->ops = pcie->drvdata->ops;
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ret = dw_pcie_host_init(pp);
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if (ret) {
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dev_err(dev, "failed to initialize host\n");
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return ret;
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}
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return 0;
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}
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static int __init ls_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct dw_pcie *pci;
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struct ls_pcie *pcie;
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struct resource *dbi_base;
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int ret;
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pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
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if (!pcie)
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return -ENOMEM;
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pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
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if (!pci)
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return -ENOMEM;
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pcie->drvdata = of_device_get_match_data(dev);
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pci->dev = dev;
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pci->ops = pcie->drvdata->dw_pcie_ops;
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pcie->pci = pci;
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dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
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pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
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if (IS_ERR(pci->dbi_base))
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return PTR_ERR(pci->dbi_base);
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pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;
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if (!ls_pcie_is_bridge(pcie))
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return -ENODEV;
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platform_set_drvdata(pdev, pcie);
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ret = ls_add_pcie_port(pcie);
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if (ret < 0)
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return ret;
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return 0;
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}
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static struct platform_driver ls_pcie_driver = {
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.driver = {
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.name = "layerscape-pcie",
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.of_match_table = ls_pcie_of_match,
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.suppress_bind_attrs = true,
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},
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};
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builtin_platform_driver_probe(ls_pcie_driver, ls_pcie_probe);
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