mirror of
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09c434b8a0
Add SPDX license identifiers to all files which:
- Have no license information of any form
- Have MODULE_LICENCE("GPL*") inside which was used in the initial
scan/conversion to ignore the file
These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:
GPL-2.0-only
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
817 lines
24 KiB
C
817 lines
24 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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*
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* Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200 and G400
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*
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* (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
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*
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* Portions Copyright (c) 2001 Matrox Graphics Inc.
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*
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* Version: 1.65 2002/08/14
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*
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* MTRR stuff: 1998 Tom Rini <trini@kernel.crashing.org>
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*
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* Contributors: "menion?" <menion@mindless.com>
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* Betatesting, fixes, ideas
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*
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* "Kurt Garloff" <garloff@suse.de>
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* Betatesting, fixes, ideas, videomodes, videomodes timmings
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*
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* "Tom Rini" <trini@kernel.crashing.org>
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* MTRR stuff, PPC cleanups, betatesting, fixes, ideas
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*
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* "Bibek Sahu" <scorpio@dodds.net>
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* Access device through readb|w|l and write b|w|l
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* Extensive debugging stuff
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*
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* "Daniel Haun" <haund@usa.net>
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* Testing, hardware cursor fixes
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*
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* "Scott Wood" <sawst46+@pitt.edu>
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* Fixes
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*
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* "Gerd Knorr" <kraxel@goldbach.isdn.cs.tu-berlin.de>
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* Betatesting
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*
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* "Kelly French" <targon@hazmat.com>
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* "Fernando Herrera" <fherrera@eurielec.etsit.upm.es>
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* Betatesting, bug reporting
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*
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* "Pablo Bianucci" <pbian@pccp.com.ar>
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* Fixes, ideas, betatesting
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*
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* "Inaky Perez Gonzalez" <inaky@peloncho.fis.ucm.es>
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* Fixes, enhandcements, ideas, betatesting
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*
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* "Ryuichi Oikawa" <roikawa@rr.iiij4u.or.jp>
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* PPC betatesting, PPC support, backward compatibility
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*
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* "Paul Womar" <Paul@pwomar.demon.co.uk>
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* "Owen Waller" <O.Waller@ee.qub.ac.uk>
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* PPC betatesting
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*
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* "Thomas Pornin" <pornin@bolet.ens.fr>
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* Alpha betatesting
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*
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* "Pieter van Leuven" <pvl@iae.nl>
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* "Ulf Jaenicke-Roessler" <ujr@physik.phy.tu-dresden.de>
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* G100 testing
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*
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* "H. Peter Arvin" <hpa@transmeta.com>
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* Ideas
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*
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* "Cort Dougan" <cort@cs.nmt.edu>
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* CHRP fixes and PReP cleanup
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*
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* "Mark Vojkovich" <mvojkovi@ucsd.edu>
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* G400 support
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*
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* "David C. Hansen" <haveblue@us.ibm.com>
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* Fixes
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*
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* "Ian Romanick" <idr@us.ibm.com>
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* Find PInS data in BIOS on PowerPC systems.
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*
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* (following author is not in any relation with this code, but his code
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* is included in this driver)
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*
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* Based on framebuffer driver for VBE 2.0 compliant graphic boards
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* (c) 1998 Gerd Knorr <kraxel@cs.tu-berlin.de>
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*
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* (following author is not in any relation with this code, but his ideas
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* were used when writing this driver)
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*
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* FreeVBE/AF (Matrox), "Shawn Hargreaves" <shawn@talula.demon.co.uk>
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*
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*/
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#include "matroxfb_misc.h"
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#include <linux/interrupt.h>
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#include <linux/matroxfb.h>
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void matroxfb_DAC_out(const struct matrox_fb_info *minfo, int reg, int val)
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{
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DBG_REG(__func__)
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mga_outb(M_RAMDAC_BASE+M_X_INDEX, reg);
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mga_outb(M_RAMDAC_BASE+M_X_DATAREG, val);
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}
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int matroxfb_DAC_in(const struct matrox_fb_info *minfo, int reg)
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{
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DBG_REG(__func__)
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mga_outb(M_RAMDAC_BASE+M_X_INDEX, reg);
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return mga_inb(M_RAMDAC_BASE+M_X_DATAREG);
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}
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void matroxfb_var2my(struct fb_var_screeninfo* var, struct my_timming* mt) {
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unsigned int pixclock = var->pixclock;
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DBG(__func__)
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if (!pixclock) pixclock = 10000; /* 10ns = 100MHz */
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mt->pixclock = 1000000000 / pixclock;
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if (mt->pixclock < 1) mt->pixclock = 1;
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mt->mnp = -1;
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mt->dblscan = var->vmode & FB_VMODE_DOUBLE;
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mt->interlaced = var->vmode & FB_VMODE_INTERLACED;
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mt->HDisplay = var->xres;
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mt->HSyncStart = mt->HDisplay + var->right_margin;
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mt->HSyncEnd = mt->HSyncStart + var->hsync_len;
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mt->HTotal = mt->HSyncEnd + var->left_margin;
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mt->VDisplay = var->yres;
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mt->VSyncStart = mt->VDisplay + var->lower_margin;
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mt->VSyncEnd = mt->VSyncStart + var->vsync_len;
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mt->VTotal = mt->VSyncEnd + var->upper_margin;
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mt->sync = var->sync;
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}
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int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int freq, unsigned int fmax,
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unsigned int* in, unsigned int* feed, unsigned int* post) {
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unsigned int bestdiff = ~0;
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unsigned int bestvco = 0;
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unsigned int fxtal = pll->ref_freq;
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unsigned int fwant;
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unsigned int p;
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DBG(__func__)
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fwant = freq;
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#ifdef DEBUG
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printk(KERN_ERR "post_shift_max: %d\n", pll->post_shift_max);
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printk(KERN_ERR "ref_freq: %d\n", pll->ref_freq);
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printk(KERN_ERR "freq: %d\n", freq);
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printk(KERN_ERR "vco_freq_min: %d\n", pll->vco_freq_min);
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printk(KERN_ERR "in_div_min: %d\n", pll->in_div_min);
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printk(KERN_ERR "in_div_max: %d\n", pll->in_div_max);
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printk(KERN_ERR "feed_div_min: %d\n", pll->feed_div_min);
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printk(KERN_ERR "feed_div_max: %d\n", pll->feed_div_max);
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printk(KERN_ERR "fmax: %d\n", fmax);
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#endif
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for (p = 1; p <= pll->post_shift_max; p++) {
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if (fwant * 2 > fmax)
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break;
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fwant *= 2;
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}
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if (fwant < pll->vco_freq_min) fwant = pll->vco_freq_min;
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if (fwant > fmax) fwant = fmax;
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for (; p-- > 0; fwant >>= 1, bestdiff >>= 1) {
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unsigned int m;
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if (fwant < pll->vco_freq_min) break;
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for (m = pll->in_div_min; m <= pll->in_div_max; m++) {
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unsigned int diff, fvco;
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unsigned int n;
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n = (fwant * (m + 1) + (fxtal >> 1)) / fxtal - 1;
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if (n > pll->feed_div_max)
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break;
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if (n < pll->feed_div_min)
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n = pll->feed_div_min;
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fvco = (fxtal * (n + 1)) / (m + 1);
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if (fvco < fwant)
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diff = fwant - fvco;
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else
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diff = fvco - fwant;
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if (diff < bestdiff) {
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bestdiff = diff;
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*post = p;
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*in = m;
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*feed = n;
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bestvco = fvco;
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}
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}
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}
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dprintk(KERN_ERR "clk: %02X %02X %02X %d %d %d\n", *in, *feed, *post, fxtal, bestvco, fwant);
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return bestvco;
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}
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int matroxfb_vgaHWinit(struct matrox_fb_info *minfo, struct my_timming *m)
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{
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unsigned int hd, hs, he, hbe, ht;
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unsigned int vd, vs, ve, vt, lc;
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unsigned int wd;
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unsigned int divider;
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int i;
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struct matrox_hw_state * const hw = &minfo->hw;
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DBG(__func__)
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hw->SEQ[0] = 0x00;
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hw->SEQ[1] = 0x01; /* or 0x09 */
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hw->SEQ[2] = 0x0F; /* bitplanes */
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hw->SEQ[3] = 0x00;
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hw->SEQ[4] = 0x0E;
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/* CRTC 0..7, 9, 16..19, 21, 22 are reprogrammed by Matrox Millennium code... Hope that by MGA1064 too */
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if (m->dblscan) {
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m->VTotal <<= 1;
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m->VDisplay <<= 1;
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m->VSyncStart <<= 1;
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m->VSyncEnd <<= 1;
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}
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if (m->interlaced) {
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m->VTotal >>= 1;
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m->VDisplay >>= 1;
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m->VSyncStart >>= 1;
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m->VSyncEnd >>= 1;
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}
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/* GCTL is ignored when not using 0xA0000 aperture */
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hw->GCTL[0] = 0x00;
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hw->GCTL[1] = 0x00;
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hw->GCTL[2] = 0x00;
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hw->GCTL[3] = 0x00;
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hw->GCTL[4] = 0x00;
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hw->GCTL[5] = 0x40;
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hw->GCTL[6] = 0x05;
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hw->GCTL[7] = 0x0F;
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hw->GCTL[8] = 0xFF;
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/* Whole ATTR is ignored in PowerGraphics mode */
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for (i = 0; i < 16; i++)
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hw->ATTR[i] = i;
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hw->ATTR[16] = 0x41;
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hw->ATTR[17] = 0xFF;
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hw->ATTR[18] = 0x0F;
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hw->ATTR[19] = 0x00;
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hw->ATTR[20] = 0x00;
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hd = m->HDisplay >> 3;
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hs = m->HSyncStart >> 3;
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he = m->HSyncEnd >> 3;
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ht = m->HTotal >> 3;
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/* standard timmings are in 8pixels, but for interleaved we cannot */
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/* do it for 4bpp (because of (4bpp >> 1(interleaved))/4 == 0) */
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/* using 16 or more pixels per unit can save us */
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divider = minfo->curr.final_bppShift;
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while (divider & 3) {
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hd >>= 1;
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hs >>= 1;
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he >>= 1;
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ht >>= 1;
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divider <<= 1;
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}
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divider = divider / 4;
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/* divider can be from 1 to 8 */
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while (divider > 8) {
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hd <<= 1;
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hs <<= 1;
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he <<= 1;
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ht <<= 1;
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divider >>= 1;
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}
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hd = hd - 1;
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hs = hs - 1;
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he = he - 1;
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ht = ht - 1;
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vd = m->VDisplay - 1;
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vs = m->VSyncStart - 1;
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ve = m->VSyncEnd - 1;
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vt = m->VTotal - 2;
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lc = vd;
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/* G200 cannot work with (ht & 7) == 6 */
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if (((ht & 0x07) == 0x06) || ((ht & 0x0F) == 0x04))
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ht++;
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hbe = ht;
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wd = minfo->fbcon.var.xres_virtual * minfo->curr.final_bppShift / 64;
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hw->CRTCEXT[0] = 0;
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hw->CRTCEXT[5] = 0;
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if (m->interlaced) {
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hw->CRTCEXT[0] = 0x80;
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hw->CRTCEXT[5] = (hs + he - ht) >> 1;
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if (!m->dblscan)
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wd <<= 1;
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vt &= ~1;
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}
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hw->CRTCEXT[0] |= (wd & 0x300) >> 4;
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hw->CRTCEXT[1] = (((ht - 4) & 0x100) >> 8) |
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((hd & 0x100) >> 7) | /* blanking */
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((hs & 0x100) >> 6) | /* sync start */
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(hbe & 0x040); /* end hor. blanking */
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/* FIXME: Enable vidrst only on G400, and only if TV-out is used */
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if (minfo->outputs[1].src == MATROXFB_SRC_CRTC1)
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hw->CRTCEXT[1] |= 0x88; /* enable horizontal and vertical vidrst */
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hw->CRTCEXT[2] = ((vt & 0xC00) >> 10) |
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((vd & 0x400) >> 8) | /* disp end */
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((vd & 0xC00) >> 7) | /* vblanking start */
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((vs & 0xC00) >> 5) |
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((lc & 0x400) >> 3);
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hw->CRTCEXT[3] = (divider - 1) | 0x80;
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hw->CRTCEXT[4] = 0;
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hw->CRTC[0] = ht-4;
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hw->CRTC[1] = hd;
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hw->CRTC[2] = hd;
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hw->CRTC[3] = (hbe & 0x1F) | 0x80;
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hw->CRTC[4] = hs;
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hw->CRTC[5] = ((hbe & 0x20) << 2) | (he & 0x1F);
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hw->CRTC[6] = vt & 0xFF;
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hw->CRTC[7] = ((vt & 0x100) >> 8) |
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((vd & 0x100) >> 7) |
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((vs & 0x100) >> 6) |
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((vd & 0x100) >> 5) |
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((lc & 0x100) >> 4) |
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((vt & 0x200) >> 4) |
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((vd & 0x200) >> 3) |
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((vs & 0x200) >> 2);
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hw->CRTC[8] = 0x00;
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hw->CRTC[9] = ((vd & 0x200) >> 4) |
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((lc & 0x200) >> 3);
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if (m->dblscan && !m->interlaced)
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hw->CRTC[9] |= 0x80;
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for (i = 10; i < 16; i++)
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hw->CRTC[i] = 0x00;
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hw->CRTC[16] = vs /* & 0xFF */;
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hw->CRTC[17] = (ve & 0x0F) | 0x20;
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hw->CRTC[18] = vd /* & 0xFF */;
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hw->CRTC[19] = wd /* & 0xFF */;
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hw->CRTC[20] = 0x00;
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hw->CRTC[21] = vd /* & 0xFF */;
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hw->CRTC[22] = (vt + 1) /* & 0xFF */;
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hw->CRTC[23] = 0xC3;
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hw->CRTC[24] = lc;
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return 0;
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};
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void matroxfb_vgaHWrestore(struct matrox_fb_info *minfo)
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{
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int i;
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struct matrox_hw_state * const hw = &minfo->hw;
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CRITFLAGS
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DBG(__func__)
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dprintk(KERN_INFO "MiscOutReg: %02X\n", hw->MiscOutReg);
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dprintk(KERN_INFO "SEQ regs: ");
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for (i = 0; i < 5; i++)
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dprintk("%02X:", hw->SEQ[i]);
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dprintk("\n");
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dprintk(KERN_INFO "GDC regs: ");
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for (i = 0; i < 9; i++)
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dprintk("%02X:", hw->GCTL[i]);
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dprintk("\n");
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dprintk(KERN_INFO "CRTC regs: ");
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for (i = 0; i < 25; i++)
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dprintk("%02X:", hw->CRTC[i]);
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dprintk("\n");
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dprintk(KERN_INFO "ATTR regs: ");
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for (i = 0; i < 21; i++)
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dprintk("%02X:", hw->ATTR[i]);
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dprintk("\n");
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CRITBEGIN
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mga_inb(M_ATTR_RESET);
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mga_outb(M_ATTR_INDEX, 0);
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mga_outb(M_MISC_REG, hw->MiscOutReg);
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for (i = 1; i < 5; i++)
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mga_setr(M_SEQ_INDEX, i, hw->SEQ[i]);
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mga_setr(M_CRTC_INDEX, 17, hw->CRTC[17] & 0x7F);
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for (i = 0; i < 25; i++)
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mga_setr(M_CRTC_INDEX, i, hw->CRTC[i]);
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for (i = 0; i < 9; i++)
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mga_setr(M_GRAPHICS_INDEX, i, hw->GCTL[i]);
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for (i = 0; i < 21; i++) {
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mga_inb(M_ATTR_RESET);
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mga_outb(M_ATTR_INDEX, i);
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mga_outb(M_ATTR_INDEX, hw->ATTR[i]);
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}
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mga_outb(M_PALETTE_MASK, 0xFF);
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mga_outb(M_DAC_REG, 0x00);
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for (i = 0; i < 768; i++)
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mga_outb(M_DAC_VAL, hw->DACpal[i]);
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mga_inb(M_ATTR_RESET);
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mga_outb(M_ATTR_INDEX, 0x20);
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CRITEND
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}
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static void get_pins(unsigned char __iomem* pins, struct matrox_bios* bd) {
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unsigned int b0 = readb(pins);
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if (b0 == 0x2E && readb(pins+1) == 0x41) {
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unsigned int pins_len = readb(pins+2);
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unsigned int i;
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unsigned char cksum;
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unsigned char* dst = bd->pins;
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if (pins_len < 3 || pins_len > 128) {
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return;
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}
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*dst++ = 0x2E;
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*dst++ = 0x41;
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*dst++ = pins_len;
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cksum = 0x2E + 0x41 + pins_len;
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for (i = 3; i < pins_len; i++) {
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cksum += *dst++ = readb(pins+i);
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}
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if (cksum) {
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return;
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}
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bd->pins_len = pins_len;
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} else if (b0 == 0x40 && readb(pins+1) == 0x00) {
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unsigned int i;
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unsigned char* dst = bd->pins;
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*dst++ = 0x40;
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*dst++ = 0;
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for (i = 2; i < 0x40; i++) {
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*dst++ = readb(pins+i);
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}
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bd->pins_len = 0x40;
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}
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}
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static void get_bios_version(unsigned char __iomem * vbios, struct matrox_bios* bd) {
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unsigned int pcir_offset;
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pcir_offset = readb(vbios + 24) | (readb(vbios + 25) << 8);
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if (pcir_offset >= 26 && pcir_offset < 0xFFE0 &&
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readb(vbios + pcir_offset ) == 'P' &&
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readb(vbios + pcir_offset + 1) == 'C' &&
|
|
readb(vbios + pcir_offset + 2) == 'I' &&
|
|
readb(vbios + pcir_offset + 3) == 'R') {
|
|
unsigned char h;
|
|
|
|
h = readb(vbios + pcir_offset + 0x12);
|
|
bd->version.vMaj = (h >> 4) & 0xF;
|
|
bd->version.vMin = h & 0xF;
|
|
bd->version.vRev = readb(vbios + pcir_offset + 0x13);
|
|
} else {
|
|
unsigned char h;
|
|
|
|
h = readb(vbios + 5);
|
|
bd->version.vMaj = (h >> 4) & 0xF;
|
|
bd->version.vMin = h & 0xF;
|
|
bd->version.vRev = 0;
|
|
}
|
|
}
|
|
|
|
static void get_bios_output(unsigned char __iomem* vbios, struct matrox_bios* bd) {
|
|
unsigned char b;
|
|
|
|
b = readb(vbios + 0x7FF1);
|
|
if (b == 0xFF) {
|
|
b = 0;
|
|
}
|
|
bd->output.state = b;
|
|
}
|
|
|
|
static void get_bios_tvout(unsigned char __iomem* vbios, struct matrox_bios* bd) {
|
|
unsigned int i;
|
|
|
|
/* Check for 'IBM .*(V....TVO' string - it means TVO BIOS */
|
|
bd->output.tvout = 0;
|
|
if (readb(vbios + 0x1D) != 'I' ||
|
|
readb(vbios + 0x1E) != 'B' ||
|
|
readb(vbios + 0x1F) != 'M' ||
|
|
readb(vbios + 0x20) != ' ') {
|
|
return;
|
|
}
|
|
for (i = 0x2D; i < 0x2D + 128; i++) {
|
|
unsigned char b = readb(vbios + i);
|
|
|
|
if (b == '(' && readb(vbios + i + 1) == 'V') {
|
|
if (readb(vbios + i + 6) == 'T' &&
|
|
readb(vbios + i + 7) == 'V' &&
|
|
readb(vbios + i + 8) == 'O') {
|
|
bd->output.tvout = 1;
|
|
}
|
|
return;
|
|
}
|
|
if (b == 0)
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void parse_bios(unsigned char __iomem* vbios, struct matrox_bios* bd) {
|
|
unsigned int pins_offset;
|
|
|
|
if (readb(vbios) != 0x55 || readb(vbios + 1) != 0xAA) {
|
|
return;
|
|
}
|
|
bd->bios_valid = 1;
|
|
get_bios_version(vbios, bd);
|
|
get_bios_output(vbios, bd);
|
|
get_bios_tvout(vbios, bd);
|
|
#if defined(__powerpc__)
|
|
/* On PowerPC cards, the PInS offset isn't stored at the end of the
|
|
* BIOS image. Instead, you must search the entire BIOS image for
|
|
* the magic PInS signature.
|
|
*
|
|
* This actually applies to all OpenFirmware base cards. Since these
|
|
* cards could be put in a MIPS or SPARC system, should the condition
|
|
* be something different?
|
|
*/
|
|
for ( pins_offset = 0 ; pins_offset <= 0xFF80 ; pins_offset++ ) {
|
|
unsigned char header[3];
|
|
|
|
header[0] = readb(vbios + pins_offset);
|
|
header[1] = readb(vbios + pins_offset + 1);
|
|
header[2] = readb(vbios + pins_offset + 2);
|
|
if ( (header[0] == 0x2E) && (header[1] == 0x41)
|
|
&& ((header[2] == 0x40) || (header[2] == 0x80)) ) {
|
|
printk(KERN_INFO "PInS data found at offset %u\n",
|
|
pins_offset);
|
|
get_pins(vbios + pins_offset, bd);
|
|
break;
|
|
}
|
|
}
|
|
#else
|
|
pins_offset = readb(vbios + 0x7FFC) | (readb(vbios + 0x7FFD) << 8);
|
|
if (pins_offset <= 0xFF80) {
|
|
get_pins(vbios + pins_offset, bd);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
static int parse_pins1(struct matrox_fb_info *minfo,
|
|
const struct matrox_bios *bd)
|
|
{
|
|
unsigned int maxdac;
|
|
|
|
switch (bd->pins[22]) {
|
|
case 0: maxdac = 175000; break;
|
|
case 1: maxdac = 220000; break;
|
|
default: maxdac = 240000; break;
|
|
}
|
|
if (get_unaligned_le16(bd->pins + 24)) {
|
|
maxdac = get_unaligned_le16(bd->pins + 24) * 10;
|
|
}
|
|
minfo->limits.pixel.vcomax = maxdac;
|
|
minfo->values.pll.system = get_unaligned_le16(bd->pins + 28) ?
|
|
get_unaligned_le16(bd->pins + 28) * 10 : 50000;
|
|
/* ignore 4MB, 8MB, module clocks */
|
|
minfo->features.pll.ref_freq = 14318;
|
|
minfo->values.reg.mctlwtst = 0x00030101;
|
|
return 0;
|
|
}
|
|
|
|
static void default_pins1(struct matrox_fb_info *minfo)
|
|
{
|
|
/* Millennium */
|
|
minfo->limits.pixel.vcomax = 220000;
|
|
minfo->values.pll.system = 50000;
|
|
minfo->features.pll.ref_freq = 14318;
|
|
minfo->values.reg.mctlwtst = 0x00030101;
|
|
}
|
|
|
|
static int parse_pins2(struct matrox_fb_info *minfo,
|
|
const struct matrox_bios *bd)
|
|
{
|
|
minfo->limits.pixel.vcomax =
|
|
minfo->limits.system.vcomax = (bd->pins[41] == 0xFF) ? 230000 : ((bd->pins[41] + 100) * 1000);
|
|
minfo->values.reg.mctlwtst = ((bd->pins[51] & 0x01) ? 0x00000001 : 0) |
|
|
((bd->pins[51] & 0x02) ? 0x00000100 : 0) |
|
|
((bd->pins[51] & 0x04) ? 0x00010000 : 0) |
|
|
((bd->pins[51] & 0x08) ? 0x00020000 : 0);
|
|
minfo->values.pll.system = (bd->pins[43] == 0xFF) ? 50000 : ((bd->pins[43] + 100) * 1000);
|
|
minfo->features.pll.ref_freq = 14318;
|
|
return 0;
|
|
}
|
|
|
|
static void default_pins2(struct matrox_fb_info *minfo)
|
|
{
|
|
/* Millennium II, Mystique */
|
|
minfo->limits.pixel.vcomax =
|
|
minfo->limits.system.vcomax = 230000;
|
|
minfo->values.reg.mctlwtst = 0x00030101;
|
|
minfo->values.pll.system = 50000;
|
|
minfo->features.pll.ref_freq = 14318;
|
|
}
|
|
|
|
static int parse_pins3(struct matrox_fb_info *minfo,
|
|
const struct matrox_bios *bd)
|
|
{
|
|
minfo->limits.pixel.vcomax =
|
|
minfo->limits.system.vcomax = (bd->pins[36] == 0xFF) ? 230000 : ((bd->pins[36] + 100) * 1000);
|
|
minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 48) == 0xFFFFFFFF ?
|
|
0x01250A21 : get_unaligned_le32(bd->pins + 48);
|
|
/* memory config */
|
|
minfo->values.reg.memrdbk = ((bd->pins[57] << 21) & 0x1E000000) |
|
|
((bd->pins[57] << 22) & 0x00C00000) |
|
|
((bd->pins[56] << 1) & 0x000001E0) |
|
|
( bd->pins[56] & 0x0000000F);
|
|
minfo->values.reg.opt = (bd->pins[54] & 7) << 10;
|
|
minfo->values.reg.opt2 = bd->pins[58] << 12;
|
|
minfo->features.pll.ref_freq = (bd->pins[52] & 0x20) ? 14318 : 27000;
|
|
return 0;
|
|
}
|
|
|
|
static void default_pins3(struct matrox_fb_info *minfo)
|
|
{
|
|
/* G100, G200 */
|
|
minfo->limits.pixel.vcomax =
|
|
minfo->limits.system.vcomax = 230000;
|
|
minfo->values.reg.mctlwtst = 0x01250A21;
|
|
minfo->values.reg.memrdbk = 0x00000000;
|
|
minfo->values.reg.opt = 0x00000C00;
|
|
minfo->values.reg.opt2 = 0x00000000;
|
|
minfo->features.pll.ref_freq = 27000;
|
|
}
|
|
|
|
static int parse_pins4(struct matrox_fb_info *minfo,
|
|
const struct matrox_bios *bd)
|
|
{
|
|
minfo->limits.pixel.vcomax = (bd->pins[ 39] == 0xFF) ? 230000 : bd->pins[ 39] * 4000;
|
|
minfo->limits.system.vcomax = (bd->pins[ 38] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 38] * 4000;
|
|
minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 71);
|
|
minfo->values.reg.memrdbk = ((bd->pins[87] << 21) & 0x1E000000) |
|
|
((bd->pins[87] << 22) & 0x00C00000) |
|
|
((bd->pins[86] << 1) & 0x000001E0) |
|
|
( bd->pins[86] & 0x0000000F);
|
|
minfo->values.reg.opt = ((bd->pins[53] << 15) & 0x00400000) |
|
|
((bd->pins[53] << 22) & 0x10000000) |
|
|
((bd->pins[53] << 7) & 0x00001C00);
|
|
minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 67);
|
|
minfo->values.pll.system = (bd->pins[ 65] == 0xFF) ? 200000 : bd->pins[ 65] * 4000;
|
|
minfo->features.pll.ref_freq = (bd->pins[ 92] & 0x01) ? 14318 : 27000;
|
|
return 0;
|
|
}
|
|
|
|
static void default_pins4(struct matrox_fb_info *minfo)
|
|
{
|
|
/* G400 */
|
|
minfo->limits.pixel.vcomax =
|
|
minfo->limits.system.vcomax = 252000;
|
|
minfo->values.reg.mctlwtst = 0x04A450A1;
|
|
minfo->values.reg.memrdbk = 0x000000E7;
|
|
minfo->values.reg.opt = 0x10000400;
|
|
minfo->values.reg.opt3 = 0x0190A419;
|
|
minfo->values.pll.system = 200000;
|
|
minfo->features.pll.ref_freq = 27000;
|
|
}
|
|
|
|
static int parse_pins5(struct matrox_fb_info *minfo,
|
|
const struct matrox_bios *bd)
|
|
{
|
|
unsigned int mult;
|
|
|
|
mult = bd->pins[4]?8000:6000;
|
|
|
|
minfo->limits.pixel.vcomax = (bd->pins[ 38] == 0xFF) ? 600000 : bd->pins[ 38] * mult;
|
|
minfo->limits.system.vcomax = (bd->pins[ 36] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 36] * mult;
|
|
minfo->limits.video.vcomax = (bd->pins[ 37] == 0xFF) ? minfo->limits.system.vcomax : bd->pins[ 37] * mult;
|
|
minfo->limits.pixel.vcomin = (bd->pins[123] == 0xFF) ? 256000 : bd->pins[123] * mult;
|
|
minfo->limits.system.vcomin = (bd->pins[121] == 0xFF) ? minfo->limits.pixel.vcomin : bd->pins[121] * mult;
|
|
minfo->limits.video.vcomin = (bd->pins[122] == 0xFF) ? minfo->limits.system.vcomin : bd->pins[122] * mult;
|
|
minfo->values.pll.system =
|
|
minfo->values.pll.video = (bd->pins[ 92] == 0xFF) ? 284000 : bd->pins[ 92] * 4000;
|
|
minfo->values.reg.opt = get_unaligned_le32(bd->pins + 48);
|
|
minfo->values.reg.opt2 = get_unaligned_le32(bd->pins + 52);
|
|
minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 94);
|
|
minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 98);
|
|
minfo->values.reg.memmisc = get_unaligned_le32(bd->pins + 102);
|
|
minfo->values.reg.memrdbk = get_unaligned_le32(bd->pins + 106);
|
|
minfo->features.pll.ref_freq = (bd->pins[110] & 0x01) ? 14318 : 27000;
|
|
minfo->values.memory.ddr = (bd->pins[114] & 0x60) == 0x20;
|
|
minfo->values.memory.dll = (bd->pins[115] & 0x02) != 0;
|
|
minfo->values.memory.emrswen = (bd->pins[115] & 0x01) != 0;
|
|
minfo->values.reg.maccess = minfo->values.memory.emrswen ? 0x00004000 : 0x00000000;
|
|
if (bd->pins[115] & 4) {
|
|
minfo->values.reg.mctlwtst_core = minfo->values.reg.mctlwtst;
|
|
} else {
|
|
u_int32_t wtst_xlat[] = { 0, 1, 5, 6, 7, 5, 2, 3 };
|
|
minfo->values.reg.mctlwtst_core = (minfo->values.reg.mctlwtst & ~7) |
|
|
wtst_xlat[minfo->values.reg.mctlwtst & 7];
|
|
}
|
|
minfo->max_pixel_clock_panellink = bd->pins[47] * 4000;
|
|
return 0;
|
|
}
|
|
|
|
static void default_pins5(struct matrox_fb_info *minfo)
|
|
{
|
|
/* Mine 16MB G450 with SDRAM DDR */
|
|
minfo->limits.pixel.vcomax =
|
|
minfo->limits.system.vcomax =
|
|
minfo->limits.video.vcomax = 600000;
|
|
minfo->limits.pixel.vcomin =
|
|
minfo->limits.system.vcomin =
|
|
minfo->limits.video.vcomin = 256000;
|
|
minfo->values.pll.system =
|
|
minfo->values.pll.video = 284000;
|
|
minfo->values.reg.opt = 0x404A1160;
|
|
minfo->values.reg.opt2 = 0x0000AC00;
|
|
minfo->values.reg.opt3 = 0x0090A409;
|
|
minfo->values.reg.mctlwtst_core =
|
|
minfo->values.reg.mctlwtst = 0x0C81462B;
|
|
minfo->values.reg.memmisc = 0x80000004;
|
|
minfo->values.reg.memrdbk = 0x01001103;
|
|
minfo->features.pll.ref_freq = 27000;
|
|
minfo->values.memory.ddr = 1;
|
|
minfo->values.memory.dll = 1;
|
|
minfo->values.memory.emrswen = 1;
|
|
minfo->values.reg.maccess = 0x00004000;
|
|
}
|
|
|
|
static int matroxfb_set_limits(struct matrox_fb_info *minfo,
|
|
const struct matrox_bios *bd)
|
|
{
|
|
unsigned int pins_version;
|
|
static const unsigned int pinslen[] = { 64, 64, 64, 128, 128 };
|
|
|
|
switch (minfo->chip) {
|
|
case MGA_2064: default_pins1(minfo); break;
|
|
case MGA_2164:
|
|
case MGA_1064:
|
|
case MGA_1164: default_pins2(minfo); break;
|
|
case MGA_G100:
|
|
case MGA_G200: default_pins3(minfo); break;
|
|
case MGA_G400: default_pins4(minfo); break;
|
|
case MGA_G450:
|
|
case MGA_G550: default_pins5(minfo); break;
|
|
}
|
|
if (!bd->bios_valid) {
|
|
printk(KERN_INFO "matroxfb: Your Matrox device does not have BIOS\n");
|
|
return -1;
|
|
}
|
|
if (bd->pins_len < 64) {
|
|
printk(KERN_INFO "matroxfb: BIOS on your Matrox device does not contain powerup info\n");
|
|
return -1;
|
|
}
|
|
if (bd->pins[0] == 0x2E && bd->pins[1] == 0x41) {
|
|
pins_version = bd->pins[5];
|
|
if (pins_version < 2 || pins_version > 5) {
|
|
printk(KERN_INFO "matroxfb: Unknown version (%u) of powerup info\n", pins_version);
|
|
return -1;
|
|
}
|
|
} else {
|
|
pins_version = 1;
|
|
}
|
|
if (bd->pins_len != pinslen[pins_version - 1]) {
|
|
printk(KERN_INFO "matroxfb: Invalid powerup info\n");
|
|
return -1;
|
|
}
|
|
switch (pins_version) {
|
|
case 1:
|
|
return parse_pins1(minfo, bd);
|
|
case 2:
|
|
return parse_pins2(minfo, bd);
|
|
case 3:
|
|
return parse_pins3(minfo, bd);
|
|
case 4:
|
|
return parse_pins4(minfo, bd);
|
|
case 5:
|
|
return parse_pins5(minfo, bd);
|
|
default:
|
|
printk(KERN_DEBUG "matroxfb: Powerup info version %u is not yet supported\n", pins_version);
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
void matroxfb_read_pins(struct matrox_fb_info *minfo)
|
|
{
|
|
u32 opt;
|
|
u32 biosbase;
|
|
u32 fbbase;
|
|
struct pci_dev *pdev = minfo->pcidev;
|
|
|
|
memset(&minfo->bios, 0, sizeof(minfo->bios));
|
|
pci_read_config_dword(pdev, PCI_OPTION_REG, &opt);
|
|
pci_write_config_dword(pdev, PCI_OPTION_REG, opt | PCI_OPTION_ENABLE_ROM);
|
|
pci_read_config_dword(pdev, PCI_ROM_ADDRESS, &biosbase);
|
|
pci_read_config_dword(pdev, minfo->devflags.fbResource, &fbbase);
|
|
pci_write_config_dword(pdev, PCI_ROM_ADDRESS, (fbbase & PCI_ROM_ADDRESS_MASK) | PCI_ROM_ADDRESS_ENABLE);
|
|
parse_bios(vaddr_va(minfo->video.vbase), &minfo->bios);
|
|
pci_write_config_dword(pdev, PCI_ROM_ADDRESS, biosbase);
|
|
pci_write_config_dword(pdev, PCI_OPTION_REG, opt);
|
|
#ifdef CONFIG_X86
|
|
if (!minfo->bios.bios_valid) {
|
|
unsigned char __iomem* b;
|
|
|
|
b = ioremap(0x000C0000, 65536);
|
|
if (!b) {
|
|
printk(KERN_INFO "matroxfb: Unable to map legacy BIOS\n");
|
|
} else {
|
|
unsigned int ven = readb(b+0x64+0) | (readb(b+0x64+1) << 8);
|
|
unsigned int dev = readb(b+0x64+2) | (readb(b+0x64+3) << 8);
|
|
|
|
if (ven != pdev->vendor || dev != pdev->device) {
|
|
printk(KERN_INFO "matroxfb: Legacy BIOS is for %04X:%04X, while this device is %04X:%04X\n",
|
|
ven, dev, pdev->vendor, pdev->device);
|
|
} else {
|
|
parse_bios(b, &minfo->bios);
|
|
}
|
|
iounmap(b);
|
|
}
|
|
}
|
|
#endif
|
|
matroxfb_set_limits(minfo, &minfo->bios);
|
|
printk(KERN_INFO "PInS memtype = %u\n",
|
|
(minfo->values.reg.opt & 0x1C00) >> 10);
|
|
}
|
|
|
|
EXPORT_SYMBOL(matroxfb_DAC_in);
|
|
EXPORT_SYMBOL(matroxfb_DAC_out);
|
|
EXPORT_SYMBOL(matroxfb_var2my);
|
|
EXPORT_SYMBOL(matroxfb_PLL_calcclock);
|
|
EXPORT_SYMBOL(matroxfb_vgaHWinit); /* DAC1064, Ti3026 */
|
|
EXPORT_SYMBOL(matroxfb_vgaHWrestore); /* DAC1064, Ti3026 */
|
|
EXPORT_SYMBOL(matroxfb_read_pins);
|
|
|
|
MODULE_AUTHOR("(c) 1999-2002 Petr Vandrovec <vandrove@vc.cvut.cz>");
|
|
MODULE_DESCRIPTION("Miscellaneous support for Matrox video cards");
|
|
MODULE_LICENSE("GPL");
|