mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-24 00:45:19 +07:00
612a9aab56
Pull drm merge (part 1) from Dave Airlie:
"So first of all my tree and uapi stuff has a conflict mess, its my
fault as the nouveau stuff didn't hit -next as were trying to rebase
regressions out of it before we merged.
Highlights:
- SH mobile modesetting driver and associated helpers
- some DRM core documentation
- i915 modesetting rework, haswell hdmi, haswell and vlv fixes, write
combined pte writing, ilk rc6 support,
- nouveau: major driver rework into a hw core driver, makes features
like SLI a lot saner to implement,
- psb: add eDP/DP support for Cedarview
- radeon: 2 layer page tables, async VM pte updates, better PLL
selection for > 2 screens, better ACPI interactions
The rest is general grab bag of fixes.
So why part 1? well I have the exynos pull req which came in a bit
late but was waiting for me to do something they shouldn't have and it
looks fairly safe, and David Howells has some more header cleanups
he'd like me to pull, that seem like a good idea, but I'd like to get
this merge out of the way so -next dosen't get blocked."
Tons of conflicts mostly due to silly include line changes, but mostly
mindless. A few other small semantic conflicts too, noted from Dave's
pre-merged branch.
* 'drm-next' of git://people.freedesktop.org/~airlied/linux: (447 commits)
drm/nv98/crypt: fix fuc build with latest envyas
drm/nouveau/devinit: fixup various issues with subdev ctor/init ordering
drm/nv41/vm: fix and enable use of "real" pciegart
drm/nv44/vm: fix and enable use of "real" pciegart
drm/nv04/dmaobj: fixup vm target handling in preparation for nv4x pcie
drm/nouveau: store supported dma mask in vmmgr
drm/nvc0/ibus: initial implementation of subdev
drm/nouveau/therm: add support for fan-control modes
drm/nouveau/hwmon: rename pwm0* to pmw1* to follow hwmon's rules
drm/nouveau/therm: calculate the pwm divisor on nv50+
drm/nouveau/fan: rewrite the fan tachometer driver to get more precision, faster
drm/nouveau/therm: move thermal-related functions to the therm subdev
drm/nouveau/bios: parse the pwm divisor from the perf table
drm/nouveau/therm: use the EXTDEV table to detect i2c monitoring devices
drm/nouveau/therm: rework thermal table parsing
drm/nouveau/gpio: expose the PWM/TOGGLE parameter found in the gpio vbios table
drm/nouveau: fix pm initialization order
drm/nouveau/bios: check that fixed tvdac gpio data is valid before using it
drm/nouveau: log channel debug/error messages from client object rather than drm client
drm/nouveau: have drm debugging macros build on top of core macros
...
72 lines
2.1 KiB
C
72 lines
2.1 KiB
C
#include <drm/drmP.h>
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#include <drm/drm_mode.h>
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#include "nouveau_drm.h"
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#include "nouveau_reg.h"
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#include "nouveau_crtc.h"
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#include "nouveau_hw.h"
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static void
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nv04_cursor_show(struct nouveau_crtc *nv_crtc, bool update)
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{
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nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, true);
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}
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static void
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nv04_cursor_hide(struct nouveau_crtc *nv_crtc, bool update)
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{
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nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, false);
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}
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static void
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nv04_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
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{
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nv_crtc->cursor_saved_x = x; nv_crtc->cursor_saved_y = y;
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NVWriteRAMDAC(nv_crtc->base.dev, nv_crtc->index,
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NV_PRAMDAC_CU_START_POS,
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XLATE(y, 0, NV_PRAMDAC_CU_START_POS_Y) |
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XLATE(x, 0, NV_PRAMDAC_CU_START_POS_X));
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}
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static void
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crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
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{
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NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,
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crtcstate->CRTC[index]);
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}
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static void
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nv04_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
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{
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struct drm_device *dev = nv_crtc->base.dev;
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struct nouveau_drm *drm = nouveau_drm(dev);
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struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
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struct drm_crtc *crtc = &nv_crtc->base;
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regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] =
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MASK(NV_CIO_CRE_HCUR_ASI) |
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XLATE(offset, 17, NV_CIO_CRE_HCUR_ADDR0_ADR);
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regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] =
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XLATE(offset, 11, NV_CIO_CRE_HCUR_ADDR1_ADR);
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if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
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regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |=
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MASK(NV_CIO_CRE_HCUR_ADDR1_CUR_DBL);
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regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = offset >> 24;
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crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
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crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
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crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
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if (nv_device(drm->device)->card_type == NV_40)
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nv_fix_nv40_hw_cursor(dev, nv_crtc->index);
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}
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int
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nv04_cursor_init(struct nouveau_crtc *crtc)
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{
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crtc->cursor.set_offset = nv04_cursor_set_offset;
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crtc->cursor.set_pos = nv04_cursor_set_pos;
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crtc->cursor.hide = nv04_cursor_hide;
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crtc->cursor.show = nv04_cursor_show;
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return 0;
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}
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