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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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338d4f49d6
'Privileged Access Never' is a new arm8.1 feature which prevents
privileged code from accessing any virtual address where read or write
access is also permitted at EL0.
This patch enables the PAN feature on all CPUs, and modifies {get,put}_user
helpers temporarily to permit access.
This will catch kernel bugs where user memory is accessed directly.
'Unprivileged loads and stores' using ldtrb et al are unaffected by PAN.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: James Morse <james.morse@arm.com>
[will: use ALTERNATIVE in asm and tidy up pan_enable check]
Signed-off-by: Will Deacon <will.deacon@arm.com>
91 lines
2.4 KiB
C
91 lines
2.4 KiB
C
/*
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* Macros for accessing system registers with older binutils.
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*
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* Copyright (C) 2014 ARM Ltd.
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* Author: Catalin Marinas <catalin.marinas@arm.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_SYSREG_H
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#define __ASM_SYSREG_H
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#include <asm/opcodes.h>
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#define SCTLR_EL1_CP15BEN (0x1 << 5)
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#define SCTLR_EL1_SED (0x1 << 8)
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/*
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* ARMv8 ARM reserves the following encoding for system registers:
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* (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
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* C5.2, version:ARM DDI 0487A.f)
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* [20-19] : Op0
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* [18-16] : Op1
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* [15-12] : CRn
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* [11-8] : CRm
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* [7-5] : Op2
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*/
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#define sys_reg(op0, op1, crn, crm, op2) \
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((((op0)&3)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5))
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#define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4)
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#define SCTLR_EL1_SPAN (1 << 23)
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#define SET_PSTATE_PAN(x) __inst_arm(0xd5000000 | REG_PSTATE_PAN_IMM |\
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(!!x)<<8 | 0x1f)
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#ifdef __ASSEMBLY__
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.irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
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.equ __reg_num_x\num, \num
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.endr
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.equ __reg_num_xzr, 31
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.macro mrs_s, rt, sreg
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.inst 0xd5200000|(\sreg)|(__reg_num_\rt)
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.endm
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.macro msr_s, sreg, rt
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.inst 0xd5000000|(\sreg)|(__reg_num_\rt)
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.endm
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#else
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asm(
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" .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"
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" .equ __reg_num_x\\num, \\num\n"
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" .endr\n"
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" .equ __reg_num_xzr, 31\n"
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"\n"
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" .macro mrs_s, rt, sreg\n"
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" .inst 0xd5200000|(\\sreg)|(__reg_num_\\rt)\n"
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" .endm\n"
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"\n"
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" .macro msr_s, sreg, rt\n"
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" .inst 0xd5000000|(\\sreg)|(__reg_num_\\rt)\n"
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" .endm\n"
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);
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static inline void config_sctlr_el1(u32 clear, u32 set)
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{
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u32 val;
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asm volatile("mrs %0, sctlr_el1" : "=r" (val));
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val &= ~clear;
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val |= set;
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asm volatile("msr sctlr_el1, %0" : : "r" (val));
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}
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#endif
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#endif /* __ASM_SYSREG_H */
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