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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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416d82204d
SEC driver provides PCIe hardware device initiation with AES, SM4, and 3DES skcipher algorithms registered to Crypto. It uses Hisilicon QM as interface to CPU. Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
61 lines
1.7 KiB
Plaintext
61 lines
1.7 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0
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config CRYPTO_DEV_HISI_SEC
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tristate "Support for Hisilicon SEC crypto block cipher accelerator"
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select CRYPTO_SKCIPHER
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select CRYPTO_ALGAPI
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select CRYPTO_LIB_DES
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select SG_SPLIT
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depends on ARM64 || COMPILE_TEST
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depends on HAS_IOMEM
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help
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Support for Hisilicon SEC Engine in Hip06 and Hip07
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To compile this as a module, choose M here: the module
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will be called hisi_sec.
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config CRYPTO_DEV_HISI_SEC2
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tristate "Support for HiSilicon SEC2 crypto block cipher accelerator"
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select CRYPTO_BLKCIPHER
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select CRYPTO_ALGAPI
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select CRYPTO_LIB_DES
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select CRYPTO_DEV_HISI_QM
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depends on PCI && PCI_MSI
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depends on ARM64 || (COMPILE_TEST && 64BIT)
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help
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Support for HiSilicon SEC Engine of version 2 in crypto subsystem.
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It provides AES, SM4, and 3DES algorithms with ECB
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CBC, and XTS cipher mode.
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To compile this as a module, choose M here: the module
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will be called hisi_sec2.
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config CRYPTO_DEV_HISI_QM
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tristate
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depends on ARM64 || COMPILE_TEST
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depends on PCI && PCI_MSI
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help
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HiSilicon accelerator engines use a common queue management
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interface. Specific engine driver may use this module.
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config CRYPTO_DEV_HISI_ZIP
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tristate "Support for HiSilicon ZIP accelerator"
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depends on PCI && PCI_MSI
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depends on ARM64 || (COMPILE_TEST && 64BIT)
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depends on !CPU_BIG_ENDIAN || COMPILE_TEST
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select CRYPTO_DEV_HISI_QM
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select SG_SPLIT
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help
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Support for HiSilicon ZIP Driver
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config CRYPTO_DEV_HISI_HPRE
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tristate "Support for HISI HPRE accelerator"
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depends on PCI && PCI_MSI
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depends on ARM64 || (COMPILE_TEST && 64BIT)
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select CRYPTO_DEV_HISI_QM
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select CRYPTO_DH
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select CRYPTO_RSA
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help
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Support for HiSilicon HPRE(High Performance RSA Engine)
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accelerator, which can accelerate RSA and DH algorithms.
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