Dirk Behme 5a5ca56e05 ARM: dts: i.MX6: configure L2 cache data and tag latency ... Configure the data and tag latency for the L2 cache. This improves the system performance. This configuration is taken from Freescale's kernel patch "ENGR00153601 [MX6]Adjust L2 cache parameter" [1] which does writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_TAG_LATENCY_CTRL)); writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_DATA_LATENCY_CTRL)); In this patch we are doing the same via the device tree. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> [1] http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_12.09.01&id=814656410b40c67a10b25300e51b0477b2bb96d1		2013-06-17 16:04:20 +08:00
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bootp	ARM: 6499/1: Thumb-2: Correct data alignment for CONFIG_THUMB2_KERNEL in bootp/init.S	2010-11-30 13:44:24 +00:00
compressed	ARM: 7750/1: update legacy CPU ID in decompressor cache support jump table	2013-06-05 23:32:40 +01:00
dts	ARM: dts: i.MX6: configure L2 cache data and tag latency	2013-06-17 16:04:20 +08:00
.gitignore	ARM: devicetree: Add .dtb files to arch/arm/boot/.gitignore	2012-01-30 11:47:37 -07:00
install.sh	kbuild: use INSTALLKERNEL to select customized installkernel script	2009-09-20 12:18:14 +02:00
Makefile	ARM: dts: remove generated .dtb files on clean	2013-03-04 17:15:35 -08:00