mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-24 13:40:53 +07:00
5a4b9fe7fe
Added tx handling in this patch. This includes handling of segments contain single complete record. v1->v2: - chcr_write_cpl_set_tcb_ulp is added in this patch. v3->v4: - mss calculation logic. - replaced kfree_skb with dev_kfree_skb_any. - corrected error message reported by kbuild test robot <lkp@intel.com> Signed-off-by: Rohit Maheshwari <rohitm@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
133 lines
3.4 KiB
C
133 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (C) 2020 Chelsio Communications. All rights reserved. */
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#ifndef __CHCR_COMMON_H__
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#define __CHCR_COMMON_H__
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#include "cxgb4.h"
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#define CHCR_MAX_SALT 4
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#define CHCR_KEYCTX_MAC_KEY_SIZE_128 0
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#define CHCR_KEYCTX_CIPHER_KEY_SIZE_128 0
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#define CHCR_SCMD_CIPHER_MODE_AES_GCM 2
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#define CHCR_CPL_TX_SEC_PDU_LEN_64BIT 2
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#define CHCR_SCMD_SEQ_NO_CTRL_64BIT 3
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#define CHCR_SCMD_PROTO_VERSION_TLS 0
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#define CHCR_SCMD_AUTH_MODE_GHASH 4
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enum chcr_state {
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CHCR_INIT = 0,
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CHCR_ATTACH,
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CHCR_DETACH,
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};
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struct chcr_dev {
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spinlock_t lock_chcr_dev; /* chcr dev structure lock */
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enum chcr_state state;
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atomic_t inflight;
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int wqretry;
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struct delayed_work detach_work;
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struct completion detach_comp;
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unsigned char tx_channel_id;
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};
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struct uld_ctx {
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struct list_head entry;
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struct cxgb4_lld_info lldi;
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struct chcr_dev dev;
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};
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struct ktls_key_ctx {
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__be32 ctx_hdr;
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u8 salt[CHCR_MAX_SALT];
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__be64 iv_to_auth;
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unsigned char key[TLS_CIPHER_AES_GCM_128_KEY_SIZE +
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TLS_CIPHER_AES_GCM_256_TAG_SIZE];
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};
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/* Crypto key context */
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#define KEY_CONTEXT_CTX_LEN_S 24
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#define KEY_CONTEXT_CTX_LEN_V(x) ((x) << KEY_CONTEXT_CTX_LEN_S)
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#define KEY_CONTEXT_SALT_PRESENT_S 10
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#define KEY_CONTEXT_SALT_PRESENT_V(x) ((x) << KEY_CONTEXT_SALT_PRESENT_S)
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#define KEY_CONTEXT_SALT_PRESENT_F KEY_CONTEXT_SALT_PRESENT_V(1U)
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#define KEY_CONTEXT_VALID_S 0
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#define KEY_CONTEXT_VALID_V(x) ((x) << KEY_CONTEXT_VALID_S)
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#define KEY_CONTEXT_VALID_F KEY_CONTEXT_VALID_V(1U)
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#define KEY_CONTEXT_CK_SIZE_S 6
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#define KEY_CONTEXT_CK_SIZE_V(x) ((x) << KEY_CONTEXT_CK_SIZE_S)
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#define KEY_CONTEXT_MK_SIZE_S 2
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#define KEY_CONTEXT_MK_SIZE_V(x) ((x) << KEY_CONTEXT_MK_SIZE_S)
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#define KEY_CONTEXT_OPAD_PRESENT_S 11
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#define KEY_CONTEXT_OPAD_PRESENT_V(x) ((x) << KEY_CONTEXT_OPAD_PRESENT_S)
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#define KEY_CONTEXT_OPAD_PRESENT_F KEY_CONTEXT_OPAD_PRESENT_V(1U)
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#define FILL_KEY_CTX_HDR(ck_size, mk_size, ctx_len) \
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htonl(KEY_CONTEXT_MK_SIZE_V(mk_size) | \
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KEY_CONTEXT_CK_SIZE_V(ck_size) | \
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KEY_CONTEXT_VALID_F | \
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KEY_CONTEXT_SALT_PRESENT_F | \
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KEY_CONTEXT_CTX_LEN_V((ctx_len)))
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struct uld_ctx *assign_chcr_device(void);
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static inline void *chcr_copy_to_txd(const void *src, const struct sge_txq *q,
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void *pos, int length)
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{
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int left = (void *)q->stat - pos;
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u64 *p;
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if (likely(length <= left)) {
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memcpy(pos, src, length);
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pos += length;
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} else {
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memcpy(pos, src, left);
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memcpy(q->desc, src + left, length - left);
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pos = (void *)q->desc + (length - left);
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}
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/* 0-pad to multiple of 16 */
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p = PTR_ALIGN(pos, 8);
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if ((uintptr_t)p & 8) {
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*p = 0;
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return p + 1;
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}
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return p;
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}
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static inline unsigned int chcr_txq_avail(const struct sge_txq *q)
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{
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return q->size - 1 - q->in_use;
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}
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static inline void chcr_txq_advance(struct sge_txq *q, unsigned int n)
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{
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q->in_use += n;
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q->pidx += n;
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if (q->pidx >= q->size)
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q->pidx -= q->size;
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}
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static inline void chcr_eth_txq_stop(struct sge_eth_txq *q)
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{
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netif_tx_stop_queue(q->txq);
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q->q.stops++;
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}
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static inline unsigned int chcr_sgl_len(unsigned int n)
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{
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n--;
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return (3 * n) / 2 + (n & 1) + 2;
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}
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static inline unsigned int chcr_flits_to_desc(unsigned int n)
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{
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WARN_ON(n > SGE_MAX_WR_LEN / 8);
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return DIV_ROUND_UP(n, 8);
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}
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#endif /* __CHCR_COMMON_H__ */
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