mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-12 05:06:39 +07:00
e5723e0eeb
This adds support for the aforementioned CPU subtypes, and cleans up some build issues encountered as a result. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
318 lines
7.0 KiB
C
318 lines
7.0 KiB
C
#ifndef __ASM_SH_IRQ_SH7343_H
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#define __ASM_SH_IRQ_SH7343_H
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/*
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* linux/include/asm-sh/irq-sh7343.h
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*
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* Copyright (C) 2006 Kenati Technologies Inc.
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* Andre Mccurdy <andre@kenati.com>
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* Ranjit Deshpande <ranjit@kenati.com>
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*/
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#undef INTC_IPRA
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#undef INTC_IPRB
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#undef INTC_IPRC
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#undef INTC_IPRD
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#undef DMTE0_IRQ
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#undef DMTE1_IRQ
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#undef DMTE2_IRQ
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#undef DMTE3_IRQ
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#undef DMTE4_IRQ
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#undef DMTE5_IRQ
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#undef DMTE6_IRQ
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#undef DMTE7_IRQ
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#undef DMAE_IRQ
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#undef DMA_IPR_ADDR
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#undef DMA_IPR_POS
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#undef DMA_PRIORITY
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#undef INTC_IMCR0
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#undef INTC_IMCR1
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#undef INTC_IMCR2
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#undef INTC_IMCR3
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#undef INTC_IMCR4
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#undef INTC_IMCR5
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#undef INTC_IMCR6
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#undef INTC_IMCR7
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#undef INTC_IMCR8
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#undef INTC_IMCR9
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#undef INTC_IMCR10
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#define INTC_IPRA 0xA4080000UL
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#define INTC_IPRB 0xA4080004UL
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#define INTC_IPRC 0xA4080008UL
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#define INTC_IPRD 0xA408000CUL
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#define INTC_IPRE 0xA4080010UL
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#define INTC_IPRF 0xA4080014UL
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#define INTC_IPRG 0xA4080018UL
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#define INTC_IPRH 0xA408001CUL
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#define INTC_IPRI 0xA4080020UL
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#define INTC_IPRJ 0xA4080024UL
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#define INTC_IPRK 0xA4080028UL
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#define INTC_IPRL 0xA408002CUL
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#define INTC_IMR0 0xA4080080UL
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#define INTC_IMR1 0xA4080084UL
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#define INTC_IMR2 0xA4080088UL
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#define INTC_IMR3 0xA408008CUL
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#define INTC_IMR4 0xA4080090UL
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#define INTC_IMR5 0xA4080094UL
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#define INTC_IMR6 0xA4080098UL
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#define INTC_IMR7 0xA408009CUL
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#define INTC_IMR8 0xA40800A0UL
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#define INTC_IMR9 0xA40800A4UL
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#define INTC_IMR10 0xA40800A8UL
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#define INTC_IMR11 0xA40800ACUL
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#define INTC_IMCR0 0xA40800C0UL
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#define INTC_IMCR1 0xA40800C4UL
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#define INTC_IMCR2 0xA40800C8UL
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#define INTC_IMCR3 0xA40800CCUL
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#define INTC_IMCR4 0xA40800D0UL
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#define INTC_IMCR5 0xA40800D4UL
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#define INTC_IMCR6 0xA40800D8UL
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#define INTC_IMCR7 0xA40800DCUL
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#define INTC_IMCR8 0xA40800E0UL
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#define INTC_IMCR9 0xA40800E4UL
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#define INTC_IMCR10 0xA40800E8UL
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#define INTC_IMCR11 0xA40800ECUL
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#define INTC_ICR0 0xA4140000UL
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#define INTC_ICR1 0xA414001CUL
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#define INTMSK0 0xa4140044
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#define INTMSKCLR0 0xa4140064
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#define INTC_INTPRI0 0xa4140010
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/*
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NOTE:
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*_IRQ = (INTEVT2 - 0x200)/0x20
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*/
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/* TMU0 */
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#define TMU0_IRQ 16
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#define TMU0_IPR_ADDR INTC_IPRA
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#define TMU0_IPR_POS 3
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#define TMU0_PRIORITY 2
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#define TIMER_IRQ 16
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#define TIMER_IPR_ADDR INTC_IPRA
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#define TIMER_IPR_POS 3
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#define TIMER_PRIORITY 2
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/* TMU1 */
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#define TMU1_IRQ 17
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#define TMU1_IPR_ADDR INTC_IPRA
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#define TMU1_IPR_POS 2
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#define TMU1_PRIORITY 2
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/* TMU2 */
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#define TMU2_IRQ 18
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#define TMU2_IPR_ADDR INTC_IPRA
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#define TMU2_IPR_POS 1
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#define TMU2_PRIORITY 2
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/* LCDC */
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#define LCDC_IRQ 28
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#define LCDC_IPR_ADDR INTC_IPRB
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#define LCDC_IPR_POS 2
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#define LCDC_PRIORITY 2
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/* VIO (Video I/O) */
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#define CEU_IRQ 52
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#define BEU_IRQ 53
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#define VEU_IRQ 54
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#define VOU_IRQ 55
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#define VIO_IPR_ADDR INTC_IPRE
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#define VIO_IPR_POS 2
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#define VIO_PRIORITY 2
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/* MFI (Multi Functional Interface) */
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#define MFI_IRQ 56
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#define MFI_IPR_ADDR INTC_IPRE
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#define MFI_IPR_POS 1
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#define MFI_PRIORITY 2
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/* VPU (Video Processing Unit) */
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#define VPU_IRQ 60
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#define VPU_IPR_ADDR INTC_IPRE
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#define VPU_IPR_POS 0
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#define VPU_PRIORITY 2
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/* 3DG */
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#define TDG_IRQ 63
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#define TDG_IPR_ADDR INTC_IPRJ
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#define TDG_IPR_POS 2
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#define TDG_PRIORITY 2
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/* DMAC(1) */
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#define DMTE0_IRQ 48
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#define DMTE1_IRQ 49
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#define DMTE2_IRQ 50
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#define DMTE3_IRQ 51
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#define DMA1_IPR_ADDR INTC_IPRE
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#define DMA1_IPR_POS 3
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#define DMA1_PRIORITY 7
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/* DMAC(2) */
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#define DMTE4_IRQ 76
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#define DMTE5_IRQ 77
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#define DMA2_IPR_ADDR INTC_IPRF
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#define DMA2_IPR_POS 2
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#define DMA2_PRIORITY 7
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/* SCIF0 */
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#define SCIF_ERI_IRQ 80
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#define SCIF_RXI_IRQ 81
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#define SCIF_BRI_IRQ 82
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#define SCIF_TXI_IRQ 83
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#define SCIF_IPR_ADDR INTC_IPRG
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#define SCIF_IPR_POS 3
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#define SCIF_PRIORITY 3
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/* SIOF0 */
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#define SIOF0_IRQ 84
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#define SIOF0_IPR_ADDR INTC_IPRH
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#define SIOF0_IPR_POS 3
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#define SIOF0_PRIORITY 3
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/* FLCTL (Flash Memory Controller) */
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#define FLSTE_IRQ 92
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#define FLTEND_IRQ 93
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#define FLTRQ0_IRQ 94
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#define FLTRQ1_IRQ 95
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#define FLCTL_IPR_ADDR INTC_IPRH
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#define FLCTL_IPR_POS 1
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#define FLCTL_PRIORITY 3
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/* IIC(0) (IIC Bus Interface) */
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#define IIC0_ALI_IRQ 96
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#define IIC0_TACKI_IRQ 97
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#define IIC0_WAITI_IRQ 98
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#define IIC0_DTEI_IRQ 99
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#define IIC0_IPR_ADDR INTC_IPRH
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#define IIC0_IPR_POS 0
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#define IIC0_PRIORITY 3
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/* IIC(1) (IIC Bus Interface) */
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#define IIC1_ALI_IRQ 44
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#define IIC1_TACKI_IRQ 45
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#define IIC1_WAITI_IRQ 46
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#define IIC1_DTEI_IRQ 47
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#define IIC1_IPR_ADDR INTC_IPRI
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#define IIC1_IPR_POS 0
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#define IIC1_PRIORITY 3
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/* SIO0 */
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#define SIO0_IRQ 88
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#define SIO0_IPR_ADDR INTC_IPRI
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#define SIO0_IPR_POS 3
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#define SIO0_PRIORITY 3
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/* SDHI */
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#define SDHI_SDHII0_IRQ 100
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#define SDHI_SDHII1_IRQ 101
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#define SDHI_SDHII2_IRQ 102
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#define SDHI_SDHII3_IRQ 103
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#define SDHI_IPR_ADDR INTC_IPRK
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#define SDHI_IPR_POS 0
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#define SDHI_PRIORITY 3
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/* SIU (Sound Interface Unit) */
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#define SIU_IRQ 108
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#define SIU_IPR_ADDR INTC_IPRJ
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#define SIU_IPR_POS 1
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#define SIU_PRIORITY 3
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#define PORT_PACR 0xA4050100UL
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#define PORT_PBCR 0xA4050102UL
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#define PORT_PCCR 0xA4050104UL
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#define PORT_PDCR 0xA4050106UL
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#define PORT_PECR 0xA4050108UL
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#define PORT_PFCR 0xA405010AUL
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#define PORT_PGCR 0xA405010CUL
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#define PORT_PHCR 0xA405010EUL
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#define PORT_PJCR 0xA4050110UL
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#define PORT_PKCR 0xA4050112UL
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#define PORT_PLCR 0xA4050114UL
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#define PORT_SCPCR 0xA4050116UL
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#define PORT_PMCR 0xA4050118UL
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#define PORT_PNCR 0xA405011AUL
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#define PORT_PQCR 0xA405011CUL
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#define PORT_PRCR 0xA405011EUL
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#define PORT_PTCR 0xA405014CUL
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#define PORT_PUCR 0xA405014EUL
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#define PORT_PVCR 0xA4050150UL
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#define PORT_PSELA 0xA4050140UL
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#define PORT_PSELB 0xA4050142UL
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#define PORT_PSELC 0xA4050144UL
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#define PORT_PSELE 0xA4050158UL
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#define PORT_HIZCRA 0xA4050146UL
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#define PORT_HIZCRB 0xA4050148UL
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#define PORT_DRVCR 0xA405014AUL
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#define PORT_PADR 0xA4050120UL
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#define PORT_PBDR 0xA4050122UL
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#define PORT_PCDR 0xA4050124UL
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#define PORT_PDDR 0xA4050126UL
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#define PORT_PEDR 0xA4050128UL
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#define PORT_PFDR 0xA405012AUL
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#define PORT_PGDR 0xA405012CUL
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#define PORT_PHDR 0xA405012EUL
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#define PORT_PJDR 0xA4050130UL
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#define PORT_PKDR 0xA4050132UL
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#define PORT_PLDR 0xA4050134UL
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#define PORT_SCPDR 0xA4050136UL
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#define PORT_PMDR 0xA4050138UL
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#define PORT_PNDR 0xA405013AUL
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#define PORT_PQDR 0xA405013CUL
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#define PORT_PRDR 0xA405013EUL
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#define PORT_PTDR 0xA405016CUL
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#define PORT_PUDR 0xA405016EUL
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#define PORT_PVDR 0xA4050170UL
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#define IRQ0_IRQ 32
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#define IRQ1_IRQ 33
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#define IRQ2_IRQ 34
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#define IRQ3_IRQ 35
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#define IRQ4_IRQ 36
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#define IRQ5_IRQ 37
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#define IRQ6_IRQ 38
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#define IRQ7_IRQ 39
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#define INTPRI00 0xA4140010UL
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#define IRQ0_IPR_ADDR INTPRI00
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#define IRQ1_IPR_ADDR INTPRI00
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#define IRQ2_IPR_ADDR INTPRI00
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#define IRQ3_IPR_ADDR INTPRI00
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#define IRQ4_IPR_ADDR INTPRI00
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#define IRQ5_IPR_ADDR INTPRI00
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#define IRQ6_IPR_ADDR INTPRI00
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#define IRQ7_IPR_ADDR INTPRI00
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#define IRQ0_IPR_POS 7
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#define IRQ1_IPR_POS 6
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#define IRQ2_IPR_POS 5
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#define IRQ3_IPR_POS 4
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#define IRQ4_IPR_POS 3
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#define IRQ5_IPR_POS 2
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#define IRQ6_IPR_POS 1
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#define IRQ7_IPR_POS 0
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#define IRQ0_PRIORITY 1
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#define IRQ1_PRIORITY 1
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#define IRQ2_PRIORITY 1
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#define IRQ3_PRIORITY 1
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#define IRQ4_PRIORITY 1
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#define IRQ5_PRIORITY 1
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#define IRQ6_PRIORITY 1
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#define IRQ7_PRIORITY 1
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#endif /* __ASM_SH_IRQ_SH7343_H */
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