mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 12:06:48 +07:00
a809d46066
With binutils 2.24 the attempt to switch with microMIPS mode to MIPS III
mode through .set mips3 results in *lots* of warnings like
{standard input}: Assembler messages:
{standard input}:397: Warning: the 64-bit MIPS architecture does not support the `smartmips' extension
during a kernel build. Fixed by using .set arch=r4000 instead.
This breaks support for building the kernel with binutils 2.13 which
was supported for 32 bit kernels only anyway and 2.14 which was a bad
vintage for MIPS anyway.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
271 lines
5.1 KiB
ArmAsm
271 lines
5.1 KiB
ArmAsm
/*
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* Copyright 2002 Embedded Edge, LLC
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* Author: dan@embeddededge.com
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*
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* Sleep helper for Au1xxx sleep mode.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <asm/asm.h>
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#include <asm/mipsregs.h>
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#include <asm/regdef.h>
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#include <asm/stackframe.h>
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.extern __flush_cache_all
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.text
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.set noreorder
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.set noat
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.align 5
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/* preparatory stuff */
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.macro SETUP_SLEEP
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subu sp, PT_SIZE
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sw $1, PT_R1(sp)
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sw $2, PT_R2(sp)
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sw $3, PT_R3(sp)
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sw $4, PT_R4(sp)
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sw $5, PT_R5(sp)
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sw $6, PT_R6(sp)
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sw $7, PT_R7(sp)
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sw $16, PT_R16(sp)
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sw $17, PT_R17(sp)
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sw $18, PT_R18(sp)
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sw $19, PT_R19(sp)
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sw $20, PT_R20(sp)
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sw $21, PT_R21(sp)
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sw $22, PT_R22(sp)
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sw $23, PT_R23(sp)
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sw $26, PT_R26(sp)
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sw $27, PT_R27(sp)
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sw $28, PT_R28(sp)
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sw $30, PT_R30(sp)
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sw $31, PT_R31(sp)
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mfc0 k0, CP0_STATUS
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sw k0, 0x20(sp)
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mfc0 k0, CP0_CONTEXT
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sw k0, 0x1c(sp)
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mfc0 k0, CP0_PAGEMASK
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sw k0, 0x18(sp)
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mfc0 k0, CP0_CONFIG
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sw k0, 0x14(sp)
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/* flush caches to make sure context is in memory */
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la t1, __flush_cache_all
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lw t0, 0(t1)
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jalr t0
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nop
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/* Now set up the scratch registers so the boot rom will
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* return to this point upon wakeup.
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* sys_scratch0 : SP
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* sys_scratch1 : RA
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*/
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lui t3, 0xb190 /* sys_xxx */
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sw sp, 0x0018(t3)
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la k0, alchemy_sleep_wakeup /* resume path */
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sw k0, 0x001c(t3)
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.endm
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.macro DO_SLEEP
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/* put power supply and processor to sleep */
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sw zero, 0x0078(t3) /* sys_slppwr */
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sync
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sw zero, 0x007c(t3) /* sys_sleep */
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sync
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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.endm
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/* sleep code for Au1000/Au1100/Au1500 memory controller type */
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LEAF(alchemy_sleep_au1000)
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SETUP_SLEEP
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/* cache following instructions, as memory gets put to sleep */
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la t0, 1f
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.set arch=r4000
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cache 0x14, 0(t0)
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cache 0x14, 32(t0)
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cache 0x14, 64(t0)
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cache 0x14, 96(t0)
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.set mips0
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1: lui a0, 0xb400 /* mem_xxx */
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sw zero, 0x001c(a0) /* Precharge */
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sync
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sw zero, 0x0020(a0) /* Auto Refresh */
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sync
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sw zero, 0x0030(a0) /* Sleep */
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sync
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DO_SLEEP
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END(alchemy_sleep_au1000)
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/* sleep code for Au1550/Au1200 memory controller type */
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LEAF(alchemy_sleep_au1550)
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SETUP_SLEEP
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/* cache following instructions, as memory gets put to sleep */
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la t0, 1f
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.set arch=r4000
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cache 0x14, 0(t0)
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cache 0x14, 32(t0)
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cache 0x14, 64(t0)
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cache 0x14, 96(t0)
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.set mips0
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1: lui a0, 0xb400 /* mem_xxx */
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sw zero, 0x08c0(a0) /* Precharge */
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sync
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sw zero, 0x08d0(a0) /* Self Refresh */
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sync
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/* wait for sdram to enter self-refresh mode */
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lui t0, 0x0100
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2: lw t1, 0x0850(a0) /* mem_sdstat */
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and t2, t1, t0
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beq t2, zero, 2b
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nop
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/* disable SDRAM clocks */
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lui t0, 0xcfff
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ori t0, t0, 0xffff
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lw t1, 0x0840(a0) /* mem_sdconfiga */
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and t1, t0, t1 /* clear CE[1:0] */
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sw t1, 0x0840(a0) /* mem_sdconfiga */
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sync
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DO_SLEEP
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END(alchemy_sleep_au1550)
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/* sleepcode for Au1300 memory controller type */
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LEAF(alchemy_sleep_au1300)
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SETUP_SLEEP
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/* cache following instructions, as memory gets put to sleep */
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la t0, 2f
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la t1, 4f
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subu t2, t1, t0
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.set arch=r4000
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1: cache 0x14, 0(t0)
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subu t2, t2, 32
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bgez t2, 1b
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addu t0, t0, 32
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.set mips0
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2: lui a0, 0xb400 /* mem_xxx */
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/* disable all ports in mem_sdportcfga */
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sw zero, 0x868(a0) /* mem_sdportcfga */
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sync
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/* disable ODT */
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li t0, 0x03010000
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sw t0, 0x08d8(a0) /* mem_sdcmd0 */
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sw t0, 0x08dc(a0) /* mem_sdcmd1 */
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sync
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/* precharge */
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li t0, 0x23000400
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sw t0, 0x08dc(a0) /* mem_sdcmd1 */
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sw t0, 0x08d8(a0) /* mem_sdcmd0 */
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sync
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/* auto refresh */
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sw zero, 0x08c8(a0) /* mem_sdautoref */
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sync
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/* block access to the DDR */
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lw t0, 0x0848(a0) /* mem_sdconfigb */
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li t1, (1 << 7 | 0x3F)
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or t0, t0, t1
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sw t0, 0x0848(a0) /* mem_sdconfigb */
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sync
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/* issue the Self Refresh command */
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li t0, 0x10000000
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sw t0, 0x08dc(a0) /* mem_sdcmd1 */
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sw t0, 0x08d8(a0) /* mem_sdcmd0 */
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sync
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/* wait for sdram to enter self-refresh mode */
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lui t0, 0x0300
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3: lw t1, 0x0850(a0) /* mem_sdstat */
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and t2, t1, t0
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bne t2, t0, 3b
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nop
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/* disable SDRAM clocks */
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li t0, ~(3<<28)
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lw t1, 0x0840(a0) /* mem_sdconfiga */
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and t1, t1, t0 /* clear CE[1:0] */
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sw t1, 0x0840(a0) /* mem_sdconfiga */
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sync
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DO_SLEEP
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4:
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END(alchemy_sleep_au1300)
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/* This is where we return upon wakeup.
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* Reload all of the registers and return.
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*/
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LEAF(alchemy_sleep_wakeup)
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lw k0, 0x20(sp)
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mtc0 k0, CP0_STATUS
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lw k0, 0x1c(sp)
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mtc0 k0, CP0_CONTEXT
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lw k0, 0x18(sp)
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mtc0 k0, CP0_PAGEMASK
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lw k0, 0x14(sp)
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mtc0 k0, CP0_CONFIG
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/* We need to catch the early Alchemy SOCs with
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* the write-only Config[OD] bit and set it back to one...
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*/
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jal au1x00_fixup_config_od
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nop
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lw $1, PT_R1(sp)
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lw $2, PT_R2(sp)
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lw $3, PT_R3(sp)
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lw $4, PT_R4(sp)
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lw $5, PT_R5(sp)
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lw $6, PT_R6(sp)
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lw $7, PT_R7(sp)
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lw $16, PT_R16(sp)
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lw $17, PT_R17(sp)
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lw $18, PT_R18(sp)
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lw $19, PT_R19(sp)
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lw $20, PT_R20(sp)
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lw $21, PT_R21(sp)
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lw $22, PT_R22(sp)
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lw $23, PT_R23(sp)
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lw $26, PT_R26(sp)
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lw $27, PT_R27(sp)
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lw $28, PT_R28(sp)
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lw $30, PT_R30(sp)
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lw $31, PT_R31(sp)
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jr ra
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addiu sp, PT_SIZE
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END(alchemy_sleep_wakeup)
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