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e11124d8ff
The r2_emul_return field in struct thread_info was used in order to take
an alternate codepath when returning to userland, which (besides not
implementing certain features) effectively used the eretnc instruction
in place of eret. The difference is that eretnc doesn't clear LLBit, and
therefore doesn't cause a linked load & store sequence to fail due to
emulation like eret would.
The reason eret would usually be used to clear LLBit is so that after
context switching we ensure that a load performed by one task doesn't
influence another task. However commit 7c151d3d5d ("MIPS: Make use of
the ERETNC instruction on MIPS R6") which introduced the r2_emul_return
field and conditional use of eretnc also for some reason began
explicitly clearing LLBit during context switches - despite retaining
the use of eret for everything but returns from the pre-r6 instruction
emulation code.
As LLBit is cleared upon context switches anyway, simplify this by using
eretnc unconditionally for MIPSr6 kernels. This allows us to remove the
4 byte r2_emul_return boolean from struct thread_info, simplify the
return to user code in entry.S and avoid the overhead of tracking &
checking state which we don't need.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14408/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
182 lines
5.9 KiB
C
182 lines
5.9 KiB
C
/* thread_info.h: MIPS low-level thread information
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*
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* Copyright (C) 2002 David Howells (dhowells@redhat.com)
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* - Incorporating suggestions made by Linus Torvalds and Dave Miller
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*/
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#ifndef _ASM_THREAD_INFO_H
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#define _ASM_THREAD_INFO_H
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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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#include <asm/processor.h>
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/*
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* low level task data that entry.S needs immediate access to
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* - this struct should fit entirely inside of one cache line
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* - this struct shares the supervisor stack pages
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* - if the contents of this structure are changed, the assembly constants
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* must also be changed
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*/
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struct thread_info {
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struct task_struct *task; /* main task structure */
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unsigned long flags; /* low level flags */
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unsigned long tp_value; /* thread pointer */
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__u32 cpu; /* current CPU */
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int preempt_count; /* 0 => preemptable, <0 => BUG */
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mm_segment_t addr_limit; /*
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* thread address space limit:
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* 0x7fffffff for user-thead
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* 0xffffffff for kernel-thread
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*/
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struct pt_regs *regs;
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long syscall; /* syscall number */
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};
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/*
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* macros/functions for gaining access to the thread information structure
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*/
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#define INIT_THREAD_INFO(tsk) \
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{ \
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.task = &tsk, \
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.flags = _TIF_FIXADE, \
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.cpu = 0, \
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.preempt_count = INIT_PREEMPT_COUNT, \
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.addr_limit = KERNEL_DS, \
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}
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#define init_thread_info (init_thread_union.thread_info)
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#define init_stack (init_thread_union.stack)
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/* How to get the thread information struct from C. */
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register struct thread_info *__current_thread_info __asm__("$28");
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static inline struct thread_info *current_thread_info(void)
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{
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return __current_thread_info;
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}
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#endif /* !__ASSEMBLY__ */
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/* thread information allocation */
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#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_32BIT)
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#define THREAD_SIZE_ORDER (1)
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#endif
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#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_64BIT)
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#define THREAD_SIZE_ORDER (2)
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#endif
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#ifdef CONFIG_PAGE_SIZE_8KB
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#define THREAD_SIZE_ORDER (1)
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#endif
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#ifdef CONFIG_PAGE_SIZE_16KB
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#define THREAD_SIZE_ORDER (0)
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#endif
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#ifdef CONFIG_PAGE_SIZE_32KB
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#define THREAD_SIZE_ORDER (0)
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#endif
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#ifdef CONFIG_PAGE_SIZE_64KB
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#define THREAD_SIZE_ORDER (0)
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#endif
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#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
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#define THREAD_MASK (THREAD_SIZE - 1UL)
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#define STACK_WARN (THREAD_SIZE / 8)
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/*
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* thread information flags
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* - these are process state flags that various assembly files may need to
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* access
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* - pending work-to-be-done flags are in LSW
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* - other flags in MSW
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*/
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#define TIF_SIGPENDING 1 /* signal pending */
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#define TIF_NEED_RESCHED 2 /* rescheduling necessary */
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#define TIF_SYSCALL_AUDIT 3 /* syscall auditing active */
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#define TIF_SECCOMP 4 /* secure computing */
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#define TIF_NOTIFY_RESUME 5 /* callback before returning to user */
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#define TIF_UPROBE 6 /* breakpointed or singlestepping */
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#define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */
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#define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */
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#define TIF_MEMDIE 18 /* is terminating due to OOM killer */
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#define TIF_NOHZ 19 /* in adaptive nohz mode */
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#define TIF_FIXADE 20 /* Fix address errors in software */
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#define TIF_LOGADE 21 /* Log address errors to syslog */
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#define TIF_32BIT_REGS 22 /* 32-bit general purpose registers */
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#define TIF_32BIT_ADDR 23 /* 32-bit address space (o32/n32) */
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#define TIF_FPUBOUND 24 /* thread bound to FPU-full CPU set */
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#define TIF_LOAD_WATCH 25 /* If set, load watch registers */
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#define TIF_SYSCALL_TRACEPOINT 26 /* syscall tracepoint instrumentation */
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#define TIF_32BIT_FPREGS 27 /* 32-bit floating point registers */
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#define TIF_HYBRID_FPREGS 28 /* 64b FP registers, odd singles in bits 63:32 of even doubles */
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#define TIF_USEDMSA 29 /* MSA has been used this quantum */
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#define TIF_MSA_CTX_LIVE 30 /* MSA context must be preserved */
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#define TIF_SYSCALL_TRACE 31 /* syscall trace active */
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#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
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#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
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#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
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#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
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#define _TIF_SECCOMP (1<<TIF_SECCOMP)
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#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
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#define _TIF_UPROBE (1<<TIF_UPROBE)
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#define _TIF_USEDFPU (1<<TIF_USEDFPU)
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#define _TIF_NOHZ (1<<TIF_NOHZ)
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#define _TIF_FIXADE (1<<TIF_FIXADE)
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#define _TIF_LOGADE (1<<TIF_LOGADE)
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#define _TIF_32BIT_REGS (1<<TIF_32BIT_REGS)
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#define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR)
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#define _TIF_FPUBOUND (1<<TIF_FPUBOUND)
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#define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH)
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#define _TIF_32BIT_FPREGS (1<<TIF_32BIT_FPREGS)
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#define _TIF_HYBRID_FPREGS (1<<TIF_HYBRID_FPREGS)
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#define _TIF_USEDMSA (1<<TIF_USEDMSA)
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#define _TIF_MSA_CTX_LIVE (1<<TIF_MSA_CTX_LIVE)
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#define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT)
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#define _TIF_WORK_SYSCALL_ENTRY (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \
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_TIF_SYSCALL_AUDIT | \
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_TIF_SYSCALL_TRACEPOINT | _TIF_SECCOMP)
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/* work to do in syscall_trace_leave() */
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#define _TIF_WORK_SYSCALL_EXIT (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \
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_TIF_SYSCALL_AUDIT | _TIF_SYSCALL_TRACEPOINT)
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/* work to do on interrupt/exception return */
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#define _TIF_WORK_MASK \
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(_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME | \
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_TIF_UPROBE)
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/* work to do on any return to u-space */
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#define _TIF_ALLWORK_MASK (_TIF_NOHZ | _TIF_WORK_MASK | \
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_TIF_WORK_SYSCALL_EXIT | \
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_TIF_SYSCALL_TRACEPOINT)
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/*
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* We stash processor id into a COP0 register to retrieve it fast
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* at kernel exception entry.
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*/
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#if defined(CONFIG_MIPS_PGD_C0_CONTEXT)
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#define SMP_CPUID_REG 20, 0 /* XCONTEXT */
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#define ASM_SMP_CPUID_REG $20
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#define SMP_CPUID_PTRSHIFT 48
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#else
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#define SMP_CPUID_REG 4, 0 /* CONTEXT */
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#define ASM_SMP_CPUID_REG $4
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#define SMP_CPUID_PTRSHIFT 23
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#endif
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#ifdef CONFIG_64BIT
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#define SMP_CPUID_REGSHIFT (SMP_CPUID_PTRSHIFT + 3)
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#else
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#define SMP_CPUID_REGSHIFT (SMP_CPUID_PTRSHIFT + 2)
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#endif
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#define ASM_CPUID_MFC0 MFC0
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#define UASM_i_CPUID_MFC0 UASM_i_MFC0
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#endif /* __KERNEL__ */
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#endif /* _ASM_THREAD_INFO_H */
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