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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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e8c24c6f5d
qcs404 has a single TSENS IP block with 10 sensors. It uses version 1.4 of the TSENS IP, functionality for which is encapsulated inside the qcom,tsens-v1 compatible. Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
194 lines
5.6 KiB
C
194 lines
5.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019, Linaro Limited
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*/
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#include <linux/bitops.h>
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#include <linux/regmap.h>
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#include <linux/delay.h>
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#include "tsens.h"
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/* ----- SROT ------ */
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#define SROT_HW_VER_OFF 0x0000
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#define SROT_CTRL_OFF 0x0004
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/* ----- TM ------ */
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#define TM_INT_EN_OFF 0x0000
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#define TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF 0x0004
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#define TM_Sn_STATUS_OFF 0x0044
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#define TM_TRDY_OFF 0x0084
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/* eeprom layout data for qcs404/405 (v1) */
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#define BASE0_MASK 0x000007f8
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#define BASE1_MASK 0x0007f800
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#define BASE0_SHIFT 3
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#define BASE1_SHIFT 11
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#define S0_P1_MASK 0x0000003f
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#define S1_P1_MASK 0x0003f000
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#define S2_P1_MASK 0x3f000000
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#define S3_P1_MASK 0x000003f0
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#define S4_P1_MASK 0x003f0000
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#define S5_P1_MASK 0x0000003f
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#define S6_P1_MASK 0x0003f000
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#define S7_P1_MASK 0x3f000000
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#define S8_P1_MASK 0x000003f0
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#define S9_P1_MASK 0x003f0000
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#define S0_P2_MASK 0x00000fc0
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#define S1_P2_MASK 0x00fc0000
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#define S2_P2_MASK_1_0 0xc0000000
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#define S2_P2_MASK_5_2 0x0000000f
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#define S3_P2_MASK 0x0000fc00
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#define S4_P2_MASK 0x0fc00000
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#define S5_P2_MASK 0x00000fc0
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#define S6_P2_MASK 0x00fc0000
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#define S7_P2_MASK_1_0 0xc0000000
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#define S7_P2_MASK_5_2 0x0000000f
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#define S8_P2_MASK 0x0000fc00
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#define S9_P2_MASK 0x0fc00000
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#define S0_P1_SHIFT 0
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#define S0_P2_SHIFT 6
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#define S1_P1_SHIFT 12
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#define S1_P2_SHIFT 18
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#define S2_P1_SHIFT 24
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#define S2_P2_SHIFT_1_0 30
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#define S2_P2_SHIFT_5_2 0
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#define S3_P1_SHIFT 4
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#define S3_P2_SHIFT 10
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#define S4_P1_SHIFT 16
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#define S4_P2_SHIFT 22
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#define S5_P1_SHIFT 0
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#define S5_P2_SHIFT 6
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#define S6_P1_SHIFT 12
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#define S6_P2_SHIFT 18
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#define S7_P1_SHIFT 24
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#define S7_P2_SHIFT_1_0 30
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#define S7_P2_SHIFT_5_2 0
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#define S8_P1_SHIFT 4
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#define S8_P2_SHIFT 10
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#define S9_P1_SHIFT 16
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#define S9_P2_SHIFT 22
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#define CAL_SEL_MASK 7
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#define CAL_SEL_SHIFT 0
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static int calibrate_v1(struct tsens_priv *priv)
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{
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u32 base0 = 0, base1 = 0;
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u32 p1[10], p2[10];
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u32 mode = 0, lsb = 0, msb = 0;
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u32 *qfprom_cdata;
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int i;
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qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib");
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if (IS_ERR(qfprom_cdata))
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return PTR_ERR(qfprom_cdata);
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mode = (qfprom_cdata[4] & CAL_SEL_MASK) >> CAL_SEL_SHIFT;
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dev_dbg(priv->dev, "calibration mode is %d\n", mode);
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switch (mode) {
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case TWO_PT_CALIB:
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base1 = (qfprom_cdata[4] & BASE1_MASK) >> BASE1_SHIFT;
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p2[0] = (qfprom_cdata[0] & S0_P2_MASK) >> S0_P2_SHIFT;
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p2[1] = (qfprom_cdata[0] & S1_P2_MASK) >> S1_P2_SHIFT;
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/* This value is split over two registers, 2 bits and 4 bits */
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lsb = (qfprom_cdata[0] & S2_P2_MASK_1_0) >> S2_P2_SHIFT_1_0;
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msb = (qfprom_cdata[1] & S2_P2_MASK_5_2) >> S2_P2_SHIFT_5_2;
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p2[2] = msb << 2 | lsb;
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p2[3] = (qfprom_cdata[1] & S3_P2_MASK) >> S3_P2_SHIFT;
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p2[4] = (qfprom_cdata[1] & S4_P2_MASK) >> S4_P2_SHIFT;
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p2[5] = (qfprom_cdata[2] & S5_P2_MASK) >> S5_P2_SHIFT;
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p2[6] = (qfprom_cdata[2] & S6_P2_MASK) >> S6_P2_SHIFT;
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/* This value is split over two registers, 2 bits and 4 bits */
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lsb = (qfprom_cdata[2] & S7_P2_MASK_1_0) >> S7_P2_SHIFT_1_0;
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msb = (qfprom_cdata[3] & S7_P2_MASK_5_2) >> S7_P2_SHIFT_5_2;
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p2[7] = msb << 2 | lsb;
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p2[8] = (qfprom_cdata[3] & S8_P2_MASK) >> S8_P2_SHIFT;
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p2[9] = (qfprom_cdata[3] & S9_P2_MASK) >> S9_P2_SHIFT;
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for (i = 0; i < priv->num_sensors; i++)
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p2[i] = ((base1 + p2[i]) << 2);
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/* Fall through */
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case ONE_PT_CALIB2:
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base0 = (qfprom_cdata[4] & BASE0_MASK) >> BASE0_SHIFT;
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p1[0] = (qfprom_cdata[0] & S0_P1_MASK) >> S0_P1_SHIFT;
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p1[1] = (qfprom_cdata[0] & S1_P1_MASK) >> S1_P1_SHIFT;
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p1[2] = (qfprom_cdata[0] & S2_P1_MASK) >> S2_P1_SHIFT;
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p1[3] = (qfprom_cdata[1] & S3_P1_MASK) >> S3_P1_SHIFT;
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p1[4] = (qfprom_cdata[1] & S4_P1_MASK) >> S4_P1_SHIFT;
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p1[5] = (qfprom_cdata[2] & S5_P1_MASK) >> S5_P1_SHIFT;
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p1[6] = (qfprom_cdata[2] & S6_P1_MASK) >> S6_P1_SHIFT;
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p1[7] = (qfprom_cdata[2] & S7_P1_MASK) >> S7_P1_SHIFT;
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p1[8] = (qfprom_cdata[3] & S8_P1_MASK) >> S8_P1_SHIFT;
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p1[9] = (qfprom_cdata[3] & S9_P1_MASK) >> S9_P1_SHIFT;
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for (i = 0; i < priv->num_sensors; i++)
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p1[i] = (((base0) + p1[i]) << 2);
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break;
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default:
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for (i = 0; i < priv->num_sensors; i++) {
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p1[i] = 500;
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p2[i] = 780;
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}
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break;
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}
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compute_intercept_slope(priv, p1, p2, mode);
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return 0;
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}
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/* v1.x: qcs404,405 */
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static const struct tsens_features tsens_v1_feat = {
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.ver_major = VER_1_X,
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.crit_int = 0,
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.adc = 1,
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.srot_split = 1,
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.max_sensors = 11,
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};
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static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = {
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/* ----- SROT ------ */
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/* VERSION */
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[VER_MAJOR] = REG_FIELD(SROT_HW_VER_OFF, 28, 31),
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[VER_MINOR] = REG_FIELD(SROT_HW_VER_OFF, 16, 27),
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[VER_STEP] = REG_FIELD(SROT_HW_VER_OFF, 0, 15),
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/* CTRL_OFFSET */
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[TSENS_EN] = REG_FIELD(SROT_CTRL_OFF, 0, 0),
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[TSENS_SW_RST] = REG_FIELD(SROT_CTRL_OFF, 1, 1),
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[SENSOR_EN] = REG_FIELD(SROT_CTRL_OFF, 3, 13),
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/* ----- TM ------ */
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/* INTERRUPT ENABLE */
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[INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 0),
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/* Sn_STATUS */
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REG_FIELD_FOR_EACH_SENSOR11(LAST_TEMP, TM_Sn_STATUS_OFF, 0, 9),
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REG_FIELD_FOR_EACH_SENSOR11(VALID, TM_Sn_STATUS_OFF, 14, 14),
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REG_FIELD_FOR_EACH_SENSOR11(MIN_STATUS, TM_Sn_STATUS_OFF, 10, 10),
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REG_FIELD_FOR_EACH_SENSOR11(LOWER_STATUS, TM_Sn_STATUS_OFF, 11, 11),
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REG_FIELD_FOR_EACH_SENSOR11(UPPER_STATUS, TM_Sn_STATUS_OFF, 12, 12),
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/* No CRITICAL field on v1.x */
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REG_FIELD_FOR_EACH_SENSOR11(MAX_STATUS, TM_Sn_STATUS_OFF, 13, 13),
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/* TRDY: 1=ready, 0=in progress */
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[TRDY] = REG_FIELD(TM_TRDY_OFF, 0, 0),
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};
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static const struct tsens_ops ops_generic_v1 = {
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.init = init_common,
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.calibrate = calibrate_v1,
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.get_temp = get_temp_tsens_valid,
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};
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const struct tsens_plat_data data_tsens_v1 = {
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.ops = &ops_generic_v1,
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.feat = &tsens_v1_feat,
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.fields = tsens_v1_regfields,
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};
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