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0eadaa9ce2
Multiple devices from the ADAU family share the same PLL structure and configuration register layout. Introduce a new helper module that can be used to calculated the PLL configuration registers based on a specified input frequency and the desired output frequency of the PLL. The ADAU1761/ADAU1781 and ADAU1373 drivers are updated to make use of this new helper module. But future drivers for additional devices from the ADAU family are also expected to make use of it. In anticipation of sharing more infrastructure code between different devices from the ADAU family the new module is called adau-utils. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mark Brown <broonie@kernel.org>
62 lines
1.2 KiB
C
62 lines
1.2 KiB
C
/*
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* Shared helper functions for devices from the ADAU family
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*
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* Copyright 2011-2016 Analog Devices Inc.
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* Author: Lars-Peter Clausen <lars@metafoo.de>
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/gcd.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include "adau-utils.h"
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int adau_calc_pll_cfg(unsigned int freq_in, unsigned int freq_out,
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uint8_t regs[5])
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{
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unsigned int r, n, m, i, j;
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unsigned int div;
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if (!freq_out) {
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r = 0;
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n = 0;
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m = 0;
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div = 0;
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} else {
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if (freq_out % freq_in != 0) {
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div = DIV_ROUND_UP(freq_in, 13500000);
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freq_in /= div;
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r = freq_out / freq_in;
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i = freq_out % freq_in;
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j = gcd(i, freq_in);
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n = i / j;
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m = freq_in / j;
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div--;
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} else {
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r = freq_out / freq_in;
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n = 0;
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m = 0;
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div = 0;
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}
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if (n > 0xffff || m > 0xffff || div > 3 || r > 8 || r < 2)
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return -EINVAL;
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}
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regs[0] = m >> 8;
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regs[1] = m & 0xff;
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regs[2] = n >> 8;
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regs[3] = n & 0xff;
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regs[4] = (r << 3) | (div << 1);
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if (m != 0)
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regs[4] |= 1; /* Fractional mode */
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return 0;
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}
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EXPORT_SYMBOL_GPL(adau_calc_pll_cfg);
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MODULE_DESCRIPTION("ASoC ADAU audio CODECs shared helper functions");
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MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
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MODULE_LICENSE("GPL v2");
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