Michal Simek 598acab44d microblaze: Define correct L1_CACHE_SHIFT value ... Microblaze cacheline length is configurable and current cpu uses two cacheline length 4 and 8. We are taking conservative maximum value to be sure that cacheline alignment is satisfied for all cases. Here is the calculation for cacheline lenght 8 32bit=4Byte values which is corresponding with SHIFT 5. Signed-off-by: Michal Simek <monstr@monstr.eu>		2010-05-06 11:21:59 +02:00
..
alpha
arm	musb: fix power field to hold all possible values	2010-04-30 09:25:07 -07:00
avr32	arch/avr32: fix build failure caused by wrong prototype	2010-04-27 16:26:03 -07:00
blackfin
cris
frv
h8300
ia64	KVM: fix the handling of dirty bitmaps to avoid overflows	2010-04-20 13:06:55 +03:00
m32r
m68k	m68knommu: fix coldfire tcdrain	2010-04-21 13:43:06 +10:00
m68knommu	m68knommu: remove a duplicate vector setting line for 68360	2010-04-21 13:43:06 +10:00
microblaze	microblaze: Define correct L1_CACHE_SHIFT value	2010-05-06 11:21:59 +02:00
mips	MIPS: Loongson 2F: Fix of problems introduced by -mfix-loongson2f-jump	2010-04-30 20:52:58 +01:00
mn10300
parisc
powerpc	Merge branch 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jwessel/linux-2.6-kgdb	2010-04-29 20:01:42 -07:00
s390	[S390] vdso: use ntp adjusted clock multiplier	2010-04-22 17:17:19 +02:00
score
sh
sparc	sparc64: Fix hardirq tracing in trap return path.	2010-04-20 00:48:37 -07:00
um	uml: Fix build breakage after slab.h changes	2010-04-19 17:46:23 +09:00
x86	Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/x86/linux-2.6-tip	2010-05-04 19:07:35 -07:00
xtensa
.gitignore
Kconfig