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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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597b046f0d
In case of SSI0 playback, SSI1 capture, SSI0 might be shared for clock output if clock master mode. Current rsnd driver had been assumed that SSI clock contiguous output which is needed for SSI parent needs SSICR::EN (SSI module enable) bit. But, this bit controls data input/output, not for clock. Clock contiguous output needs SSICR : FORCE, SCKD, SWSD, and SSIWSR : CONT. Not SSICR : EN. Because of this wrong assumption, and insufficient control, on current code, for example, if it starts SSI0(playback) -> SSI1(capture) order, SSI0 SSICR::EN bit will temporarily be 0. It causes playback side underrun error. This is bug. We can reproduce this issue with SSI+SRC (without DVC), and capture during playback operation. This patch fixup current (wrong) assumption, and control SSICR::EN bit correctly. Reported-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Mark Brown <broonie@kernel.org> |
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| .. | ||
| adg.c | ||
| cmd.c | ||
| core.c | ||
| ctu.c | ||
| dma.c | ||
| dvc.c | ||
| gen.c | ||
| Makefile | ||
| mix.c | ||
| rsnd.h | ||
| src.c | ||
| ssi.c | ||
| ssiu.c | ||