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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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5d18ee67d4
Currently the driver doesn't support completion vectors. These are used to indicate which sets of CQs should be grouped together into the same vector. A vector is a CQ processing thread that runs on a specific CPU. If an application has several CQs bound to different completion vectors, and each completion vector runs on different CPUs, then the completion queue workload is balanced. This helps scale as more nodes are used. Implement CQ completion vector support using a global workqueue where a CQ entry is queued to the CPU corresponding to the CQ's completion vector. Since the workqueue is global, it's guaranteed to always be there when queueing CQ entries; Therefore, the RCU locking for cq->rdi->worker in the hot path is superfluous. Each completion vector is assigned to a different CPU. The number of completion vectors available is computed by taking the number of online, physical CPUs from the local NUMA node and subtracting the CPUs used for kernel receive queues and the general interrupt. Special use cases: * If there are no CPUs left for completion vectors, the same CPU for the general interrupt is used; Therefore, there would only be one completion vector available. * For multi-HFI systems, the number of completion vectors available for each device is the total number of completion vectors in the local NUMA node divided by the number of devices in the same NUMA node. If there's a division remainder, the first device to get initialized gets an extra completion vector. Upon a CQ creation, an invalid completion vector could be specified. Handle it as follows: * If the completion vector is less than 0, set it to 0. * Set the completion vector to the result of the passed completion vector moded with the number of device completion vectors available. Reviewed-by: Mike Marciniszyn <mike.marciniszyn@intel.com> Signed-off-by: Sebastian Sanchez <sebastian.sanchez@intel.com> Signed-off-by: Dennis Dalessandro <dennis.dalessandro@intel.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
1215 lines
32 KiB
C
1215 lines
32 KiB
C
/*
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* Copyright(c) 2015 - 2018 Intel Corporation.
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* BSD LICENSE
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* - Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <linux/topology.h>
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#include <linux/cpumask.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include "hfi.h"
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#include "affinity.h"
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#include "sdma.h"
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#include "trace.h"
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struct hfi1_affinity_node_list node_affinity = {
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.list = LIST_HEAD_INIT(node_affinity.list),
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.lock = __MUTEX_INITIALIZER(node_affinity.lock)
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};
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/* Name of IRQ types, indexed by enum irq_type */
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static const char * const irq_type_names[] = {
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"SDMA",
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"RCVCTXT",
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"GENERAL",
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"OTHER",
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};
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/* Per NUMA node count of HFI devices */
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static unsigned int *hfi1_per_node_cntr;
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static inline void init_cpu_mask_set(struct cpu_mask_set *set)
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{
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cpumask_clear(&set->mask);
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cpumask_clear(&set->used);
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set->gen = 0;
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}
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/* Increment generation of CPU set if needed */
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static void _cpu_mask_set_gen_inc(struct cpu_mask_set *set)
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{
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if (cpumask_equal(&set->mask, &set->used)) {
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/*
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* We've used up all the CPUs, bump up the generation
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* and reset the 'used' map
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*/
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set->gen++;
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cpumask_clear(&set->used);
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}
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}
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static void _cpu_mask_set_gen_dec(struct cpu_mask_set *set)
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{
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if (cpumask_empty(&set->used) && set->gen) {
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set->gen--;
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cpumask_copy(&set->used, &set->mask);
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}
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}
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/* Get the first CPU from the list of unused CPUs in a CPU set data structure */
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static int cpu_mask_set_get_first(struct cpu_mask_set *set, cpumask_var_t diff)
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{
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int cpu;
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if (!diff || !set)
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return -EINVAL;
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_cpu_mask_set_gen_inc(set);
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/* Find out CPUs left in CPU mask */
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cpumask_andnot(diff, &set->mask, &set->used);
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cpu = cpumask_first(diff);
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if (cpu >= nr_cpu_ids) /* empty */
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cpu = -EINVAL;
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else
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cpumask_set_cpu(cpu, &set->used);
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return cpu;
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}
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static void cpu_mask_set_put(struct cpu_mask_set *set, int cpu)
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{
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if (!set)
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return;
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cpumask_clear_cpu(cpu, &set->used);
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_cpu_mask_set_gen_dec(set);
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}
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/* Initialize non-HT cpu cores mask */
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void init_real_cpu_mask(void)
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{
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int possible, curr_cpu, i, ht;
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cpumask_clear(&node_affinity.real_cpu_mask);
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/* Start with cpu online mask as the real cpu mask */
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cpumask_copy(&node_affinity.real_cpu_mask, cpu_online_mask);
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/*
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* Remove HT cores from the real cpu mask. Do this in two steps below.
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*/
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possible = cpumask_weight(&node_affinity.real_cpu_mask);
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ht = cpumask_weight(topology_sibling_cpumask(
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cpumask_first(&node_affinity.real_cpu_mask)));
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/*
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* Step 1. Skip over the first N HT siblings and use them as the
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* "real" cores. Assumes that HT cores are not enumerated in
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* succession (except in the single core case).
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*/
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curr_cpu = cpumask_first(&node_affinity.real_cpu_mask);
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for (i = 0; i < possible / ht; i++)
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curr_cpu = cpumask_next(curr_cpu, &node_affinity.real_cpu_mask);
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/*
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* Step 2. Remove the remaining HT siblings. Use cpumask_next() to
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* skip any gaps.
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*/
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for (; i < possible; i++) {
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cpumask_clear_cpu(curr_cpu, &node_affinity.real_cpu_mask);
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curr_cpu = cpumask_next(curr_cpu, &node_affinity.real_cpu_mask);
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}
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}
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int node_affinity_init(void)
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{
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int node;
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struct pci_dev *dev = NULL;
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const struct pci_device_id *ids = hfi1_pci_tbl;
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cpumask_clear(&node_affinity.proc.used);
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cpumask_copy(&node_affinity.proc.mask, cpu_online_mask);
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node_affinity.proc.gen = 0;
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node_affinity.num_core_siblings =
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cpumask_weight(topology_sibling_cpumask(
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cpumask_first(&node_affinity.proc.mask)
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));
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node_affinity.num_possible_nodes = num_possible_nodes();
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node_affinity.num_online_nodes = num_online_nodes();
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node_affinity.num_online_cpus = num_online_cpus();
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/*
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* The real cpu mask is part of the affinity struct but it has to be
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* initialized early. It is needed to calculate the number of user
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* contexts in set_up_context_variables().
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*/
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init_real_cpu_mask();
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hfi1_per_node_cntr = kcalloc(node_affinity.num_possible_nodes,
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sizeof(*hfi1_per_node_cntr), GFP_KERNEL);
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if (!hfi1_per_node_cntr)
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return -ENOMEM;
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while (ids->vendor) {
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dev = NULL;
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while ((dev = pci_get_device(ids->vendor, ids->device, dev))) {
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node = pcibus_to_node(dev->bus);
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if (node < 0)
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node = numa_node_id();
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hfi1_per_node_cntr[node]++;
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}
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ids++;
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}
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return 0;
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}
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static void node_affinity_destroy(struct hfi1_affinity_node *entry)
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{
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free_percpu(entry->comp_vect_affinity);
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kfree(entry);
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}
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void node_affinity_destroy_all(void)
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{
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struct list_head *pos, *q;
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struct hfi1_affinity_node *entry;
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mutex_lock(&node_affinity.lock);
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list_for_each_safe(pos, q, &node_affinity.list) {
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entry = list_entry(pos, struct hfi1_affinity_node,
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list);
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list_del(pos);
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node_affinity_destroy(entry);
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}
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mutex_unlock(&node_affinity.lock);
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kfree(hfi1_per_node_cntr);
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}
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static struct hfi1_affinity_node *node_affinity_allocate(int node)
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{
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struct hfi1_affinity_node *entry;
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entry = kzalloc(sizeof(*entry), GFP_KERNEL);
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if (!entry)
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return NULL;
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entry->node = node;
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entry->comp_vect_affinity = alloc_percpu(u16);
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INIT_LIST_HEAD(&entry->list);
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return entry;
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}
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/*
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* It appends an entry to the list.
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* It *must* be called with node_affinity.lock held.
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*/
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static void node_affinity_add_tail(struct hfi1_affinity_node *entry)
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{
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list_add_tail(&entry->list, &node_affinity.list);
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}
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/* It must be called with node_affinity.lock held */
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static struct hfi1_affinity_node *node_affinity_lookup(int node)
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{
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struct list_head *pos;
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struct hfi1_affinity_node *entry;
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list_for_each(pos, &node_affinity.list) {
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entry = list_entry(pos, struct hfi1_affinity_node, list);
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if (entry->node == node)
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return entry;
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}
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return NULL;
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}
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static int per_cpu_affinity_get(cpumask_var_t possible_cpumask,
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u16 __percpu *comp_vect_affinity)
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{
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int curr_cpu;
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u16 cntr;
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u16 prev_cntr;
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int ret_cpu;
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if (!possible_cpumask) {
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ret_cpu = -EINVAL;
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goto fail;
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}
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if (!comp_vect_affinity) {
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ret_cpu = -EINVAL;
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goto fail;
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}
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ret_cpu = cpumask_first(possible_cpumask);
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if (ret_cpu >= nr_cpu_ids) {
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ret_cpu = -EINVAL;
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goto fail;
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}
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prev_cntr = *per_cpu_ptr(comp_vect_affinity, ret_cpu);
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for_each_cpu(curr_cpu, possible_cpumask) {
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cntr = *per_cpu_ptr(comp_vect_affinity, curr_cpu);
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if (cntr < prev_cntr) {
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ret_cpu = curr_cpu;
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prev_cntr = cntr;
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}
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}
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*per_cpu_ptr(comp_vect_affinity, ret_cpu) += 1;
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fail:
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return ret_cpu;
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}
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static int per_cpu_affinity_put_max(cpumask_var_t possible_cpumask,
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u16 __percpu *comp_vect_affinity)
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{
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int curr_cpu;
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int max_cpu;
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u16 cntr;
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u16 prev_cntr;
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if (!possible_cpumask)
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return -EINVAL;
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if (!comp_vect_affinity)
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return -EINVAL;
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max_cpu = cpumask_first(possible_cpumask);
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if (max_cpu >= nr_cpu_ids)
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return -EINVAL;
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prev_cntr = *per_cpu_ptr(comp_vect_affinity, max_cpu);
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for_each_cpu(curr_cpu, possible_cpumask) {
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cntr = *per_cpu_ptr(comp_vect_affinity, curr_cpu);
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if (cntr > prev_cntr) {
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max_cpu = curr_cpu;
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prev_cntr = cntr;
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}
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}
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*per_cpu_ptr(comp_vect_affinity, max_cpu) -= 1;
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return max_cpu;
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}
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/*
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* Non-interrupt CPUs are used first, then interrupt CPUs.
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* Two already allocated cpu masks must be passed.
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*/
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static int _dev_comp_vect_cpu_get(struct hfi1_devdata *dd,
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struct hfi1_affinity_node *entry,
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cpumask_var_t non_intr_cpus,
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cpumask_var_t available_cpus)
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__must_hold(&node_affinity.lock)
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{
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int cpu;
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struct cpu_mask_set *set = dd->comp_vect;
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lockdep_assert_held(&node_affinity.lock);
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if (!non_intr_cpus) {
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cpu = -1;
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goto fail;
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}
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|
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if (!available_cpus) {
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cpu = -1;
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goto fail;
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}
|
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|
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/* Available CPUs for pinning completion vectors */
|
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_cpu_mask_set_gen_inc(set);
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cpumask_andnot(available_cpus, &set->mask, &set->used);
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|
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/* Available CPUs without SDMA engine interrupts */
|
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cpumask_andnot(non_intr_cpus, available_cpus,
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&entry->def_intr.used);
|
|
|
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/* If there are non-interrupt CPUs available, use them first */
|
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if (!cpumask_empty(non_intr_cpus))
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cpu = cpumask_first(non_intr_cpus);
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else /* Otherwise, use interrupt CPUs */
|
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cpu = cpumask_first(available_cpus);
|
|
|
|
if (cpu >= nr_cpu_ids) { /* empty */
|
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cpu = -1;
|
|
goto fail;
|
|
}
|
|
cpumask_set_cpu(cpu, &set->used);
|
|
|
|
fail:
|
|
return cpu;
|
|
}
|
|
|
|
static void _dev_comp_vect_cpu_put(struct hfi1_devdata *dd, int cpu)
|
|
{
|
|
struct cpu_mask_set *set = dd->comp_vect;
|
|
|
|
if (cpu < 0)
|
|
return;
|
|
|
|
cpu_mask_set_put(set, cpu);
|
|
}
|
|
|
|
/* _dev_comp_vect_mappings_destroy() is reentrant */
|
|
static void _dev_comp_vect_mappings_destroy(struct hfi1_devdata *dd)
|
|
{
|
|
int i, cpu;
|
|
|
|
if (!dd->comp_vect_mappings)
|
|
return;
|
|
|
|
for (i = 0; i < dd->comp_vect_possible_cpus; i++) {
|
|
cpu = dd->comp_vect_mappings[i];
|
|
_dev_comp_vect_cpu_put(dd, cpu);
|
|
dd->comp_vect_mappings[i] = -1;
|
|
hfi1_cdbg(AFFINITY,
|
|
"[%s] Release CPU %d from completion vector %d",
|
|
rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), cpu, i);
|
|
}
|
|
|
|
kfree(dd->comp_vect_mappings);
|
|
dd->comp_vect_mappings = NULL;
|
|
}
|
|
|
|
/*
|
|
* This function creates the table for looking up CPUs for completion vectors.
|
|
* num_comp_vectors needs to have been initilized before calling this function.
|
|
*/
|
|
static int _dev_comp_vect_mappings_create(struct hfi1_devdata *dd,
|
|
struct hfi1_affinity_node *entry)
|
|
__must_hold(&node_affinity.lock)
|
|
{
|
|
int i, cpu, ret;
|
|
cpumask_var_t non_intr_cpus;
|
|
cpumask_var_t available_cpus;
|
|
|
|
lockdep_assert_held(&node_affinity.lock);
|
|
|
|
if (!zalloc_cpumask_var(&non_intr_cpus, GFP_KERNEL))
|
|
return -ENOMEM;
|
|
|
|
if (!zalloc_cpumask_var(&available_cpus, GFP_KERNEL)) {
|
|
free_cpumask_var(non_intr_cpus);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
dd->comp_vect_mappings = kcalloc(dd->comp_vect_possible_cpus,
|
|
sizeof(*dd->comp_vect_mappings),
|
|
GFP_KERNEL);
|
|
if (!dd->comp_vect_mappings) {
|
|
ret = -ENOMEM;
|
|
goto fail;
|
|
}
|
|
for (i = 0; i < dd->comp_vect_possible_cpus; i++)
|
|
dd->comp_vect_mappings[i] = -1;
|
|
|
|
for (i = 0; i < dd->comp_vect_possible_cpus; i++) {
|
|
cpu = _dev_comp_vect_cpu_get(dd, entry, non_intr_cpus,
|
|
available_cpus);
|
|
if (cpu < 0) {
|
|
ret = -EINVAL;
|
|
goto fail;
|
|
}
|
|
|
|
dd->comp_vect_mappings[i] = cpu;
|
|
hfi1_cdbg(AFFINITY,
|
|
"[%s] Completion Vector %d -> CPU %d",
|
|
rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), i, cpu);
|
|
}
|
|
|
|
return 0;
|
|
|
|
fail:
|
|
free_cpumask_var(available_cpus);
|
|
free_cpumask_var(non_intr_cpus);
|
|
_dev_comp_vect_mappings_destroy(dd);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int hfi1_comp_vectors_set_up(struct hfi1_devdata *dd)
|
|
{
|
|
int ret;
|
|
struct hfi1_affinity_node *entry;
|
|
|
|
mutex_lock(&node_affinity.lock);
|
|
entry = node_affinity_lookup(dd->node);
|
|
if (!entry) {
|
|
ret = -EINVAL;
|
|
goto unlock;
|
|
}
|
|
ret = _dev_comp_vect_mappings_create(dd, entry);
|
|
unlock:
|
|
mutex_unlock(&node_affinity.lock);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void hfi1_comp_vectors_clean_up(struct hfi1_devdata *dd)
|
|
{
|
|
_dev_comp_vect_mappings_destroy(dd);
|
|
}
|
|
|
|
int hfi1_comp_vect_mappings_lookup(struct rvt_dev_info *rdi, int comp_vect)
|
|
{
|
|
struct hfi1_ibdev *verbs_dev = dev_from_rdi(rdi);
|
|
struct hfi1_devdata *dd = dd_from_dev(verbs_dev);
|
|
|
|
if (!dd->comp_vect_mappings)
|
|
return -EINVAL;
|
|
if (comp_vect >= dd->comp_vect_possible_cpus)
|
|
return -EINVAL;
|
|
|
|
return dd->comp_vect_mappings[comp_vect];
|
|
}
|
|
|
|
/*
|
|
* It assumes dd->comp_vect_possible_cpus is available.
|
|
*/
|
|
static int _dev_comp_vect_cpu_mask_init(struct hfi1_devdata *dd,
|
|
struct hfi1_affinity_node *entry,
|
|
bool first_dev_init)
|
|
__must_hold(&node_affinity.lock)
|
|
{
|
|
int i, j, curr_cpu;
|
|
int possible_cpus_comp_vect = 0;
|
|
struct cpumask *dev_comp_vect_mask = &dd->comp_vect->mask;
|
|
|
|
lockdep_assert_held(&node_affinity.lock);
|
|
/*
|
|
* If there's only one CPU available for completion vectors, then
|
|
* there will only be one completion vector available. Othewise,
|
|
* the number of completion vector available will be the number of
|
|
* available CPUs divide it by the number of devices in the
|
|
* local NUMA node.
|
|
*/
|
|
if (cpumask_weight(&entry->comp_vect_mask) == 1) {
|
|
possible_cpus_comp_vect = 1;
|
|
dd_dev_warn(dd,
|
|
"Number of kernel receive queues is too large for completion vector affinity to be effective\n");
|
|
} else {
|
|
possible_cpus_comp_vect +=
|
|
cpumask_weight(&entry->comp_vect_mask) /
|
|
hfi1_per_node_cntr[dd->node];
|
|
|
|
/*
|
|
* If the completion vector CPUs available doesn't divide
|
|
* evenly among devices, then the first device device to be
|
|
* initialized gets an extra CPU.
|
|
*/
|
|
if (first_dev_init &&
|
|
cpumask_weight(&entry->comp_vect_mask) %
|
|
hfi1_per_node_cntr[dd->node] != 0)
|
|
possible_cpus_comp_vect++;
|
|
}
|
|
|
|
dd->comp_vect_possible_cpus = possible_cpus_comp_vect;
|
|
|
|
/* Reserving CPUs for device completion vector */
|
|
for (i = 0; i < dd->comp_vect_possible_cpus; i++) {
|
|
curr_cpu = per_cpu_affinity_get(&entry->comp_vect_mask,
|
|
entry->comp_vect_affinity);
|
|
if (curr_cpu < 0)
|
|
goto fail;
|
|
|
|
cpumask_set_cpu(curr_cpu, dev_comp_vect_mask);
|
|
}
|
|
|
|
hfi1_cdbg(AFFINITY,
|
|
"[%s] Completion vector affinity CPU set(s) %*pbl",
|
|
rvt_get_ibdev_name(&(dd)->verbs_dev.rdi),
|
|
cpumask_pr_args(dev_comp_vect_mask));
|
|
|
|
return 0;
|
|
|
|
fail:
|
|
for (j = 0; j < i; j++)
|
|
per_cpu_affinity_put_max(&entry->comp_vect_mask,
|
|
entry->comp_vect_affinity);
|
|
|
|
return curr_cpu;
|
|
}
|
|
|
|
/*
|
|
* It assumes dd->comp_vect_possible_cpus is available.
|
|
*/
|
|
static void _dev_comp_vect_cpu_mask_clean_up(struct hfi1_devdata *dd,
|
|
struct hfi1_affinity_node *entry)
|
|
__must_hold(&node_affinity.lock)
|
|
{
|
|
int i, cpu;
|
|
|
|
lockdep_assert_held(&node_affinity.lock);
|
|
if (!dd->comp_vect_possible_cpus)
|
|
return;
|
|
|
|
for (i = 0; i < dd->comp_vect_possible_cpus; i++) {
|
|
cpu = per_cpu_affinity_put_max(&dd->comp_vect->mask,
|
|
entry->comp_vect_affinity);
|
|
/* Clearing CPU in device completion vector cpu mask */
|
|
if (cpu >= 0)
|
|
cpumask_clear_cpu(cpu, &dd->comp_vect->mask);
|
|
}
|
|
|
|
dd->comp_vect_possible_cpus = 0;
|
|
}
|
|
|
|
/*
|
|
* Interrupt affinity.
|
|
*
|
|
* non-rcv avail gets a default mask that
|
|
* starts as possible cpus with threads reset
|
|
* and each rcv avail reset.
|
|
*
|
|
* rcv avail gets node relative 1 wrapping back
|
|
* to the node relative 1 as necessary.
|
|
*
|
|
*/
|
|
int hfi1_dev_affinity_init(struct hfi1_devdata *dd)
|
|
{
|
|
int node = pcibus_to_node(dd->pcidev->bus);
|
|
struct hfi1_affinity_node *entry;
|
|
const struct cpumask *local_mask;
|
|
int curr_cpu, possible, i, ret;
|
|
bool new_entry = false;
|
|
|
|
if (node < 0)
|
|
node = numa_node_id();
|
|
dd->node = node;
|
|
|
|
local_mask = cpumask_of_node(dd->node);
|
|
if (cpumask_first(local_mask) >= nr_cpu_ids)
|
|
local_mask = topology_core_cpumask(0);
|
|
|
|
mutex_lock(&node_affinity.lock);
|
|
entry = node_affinity_lookup(dd->node);
|
|
|
|
/*
|
|
* If this is the first time this NUMA node's affinity is used,
|
|
* create an entry in the global affinity structure and initialize it.
|
|
*/
|
|
if (!entry) {
|
|
entry = node_affinity_allocate(node);
|
|
if (!entry) {
|
|
dd_dev_err(dd,
|
|
"Unable to allocate global affinity node\n");
|
|
ret = -ENOMEM;
|
|
goto fail;
|
|
}
|
|
new_entry = true;
|
|
|
|
init_cpu_mask_set(&entry->def_intr);
|
|
init_cpu_mask_set(&entry->rcv_intr);
|
|
cpumask_clear(&entry->comp_vect_mask);
|
|
cpumask_clear(&entry->general_intr_mask);
|
|
/* Use the "real" cpu mask of this node as the default */
|
|
cpumask_and(&entry->def_intr.mask, &node_affinity.real_cpu_mask,
|
|
local_mask);
|
|
|
|
/* fill in the receive list */
|
|
possible = cpumask_weight(&entry->def_intr.mask);
|
|
curr_cpu = cpumask_first(&entry->def_intr.mask);
|
|
|
|
if (possible == 1) {
|
|
/* only one CPU, everyone will use it */
|
|
cpumask_set_cpu(curr_cpu, &entry->rcv_intr.mask);
|
|
cpumask_set_cpu(curr_cpu, &entry->general_intr_mask);
|
|
} else {
|
|
/*
|
|
* The general/control context will be the first CPU in
|
|
* the default list, so it is removed from the default
|
|
* list and added to the general interrupt list.
|
|
*/
|
|
cpumask_clear_cpu(curr_cpu, &entry->def_intr.mask);
|
|
cpumask_set_cpu(curr_cpu, &entry->general_intr_mask);
|
|
curr_cpu = cpumask_next(curr_cpu,
|
|
&entry->def_intr.mask);
|
|
|
|
/*
|
|
* Remove the remaining kernel receive queues from
|
|
* the default list and add them to the receive list.
|
|
*/
|
|
for (i = 0;
|
|
i < (dd->n_krcv_queues - 1) *
|
|
hfi1_per_node_cntr[dd->node];
|
|
i++) {
|
|
cpumask_clear_cpu(curr_cpu,
|
|
&entry->def_intr.mask);
|
|
cpumask_set_cpu(curr_cpu,
|
|
&entry->rcv_intr.mask);
|
|
curr_cpu = cpumask_next(curr_cpu,
|
|
&entry->def_intr.mask);
|
|
if (curr_cpu >= nr_cpu_ids)
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* If there ends up being 0 CPU cores leftover for SDMA
|
|
* engines, use the same CPU cores as general/control
|
|
* context.
|
|
*/
|
|
if (cpumask_weight(&entry->def_intr.mask) == 0)
|
|
cpumask_copy(&entry->def_intr.mask,
|
|
&entry->general_intr_mask);
|
|
}
|
|
|
|
/* Determine completion vector CPUs for the entire node */
|
|
cpumask_and(&entry->comp_vect_mask,
|
|
&node_affinity.real_cpu_mask, local_mask);
|
|
cpumask_andnot(&entry->comp_vect_mask,
|
|
&entry->comp_vect_mask,
|
|
&entry->rcv_intr.mask);
|
|
cpumask_andnot(&entry->comp_vect_mask,
|
|
&entry->comp_vect_mask,
|
|
&entry->general_intr_mask);
|
|
|
|
/*
|
|
* If there ends up being 0 CPU cores leftover for completion
|
|
* vectors, use the same CPU core as the general/control
|
|
* context.
|
|
*/
|
|
if (cpumask_weight(&entry->comp_vect_mask) == 0)
|
|
cpumask_copy(&entry->comp_vect_mask,
|
|
&entry->general_intr_mask);
|
|
}
|
|
|
|
ret = _dev_comp_vect_cpu_mask_init(dd, entry, new_entry);
|
|
if (ret < 0)
|
|
goto fail;
|
|
|
|
if (new_entry)
|
|
node_affinity_add_tail(entry);
|
|
|
|
mutex_unlock(&node_affinity.lock);
|
|
|
|
return 0;
|
|
|
|
fail:
|
|
if (new_entry)
|
|
node_affinity_destroy(entry);
|
|
mutex_unlock(&node_affinity.lock);
|
|
return ret;
|
|
}
|
|
|
|
void hfi1_dev_affinity_clean_up(struct hfi1_devdata *dd)
|
|
{
|
|
struct hfi1_affinity_node *entry;
|
|
|
|
if (dd->node < 0)
|
|
return;
|
|
|
|
mutex_lock(&node_affinity.lock);
|
|
entry = node_affinity_lookup(dd->node);
|
|
if (!entry)
|
|
goto unlock;
|
|
|
|
/*
|
|
* Free device completion vector CPUs to be used by future
|
|
* completion vectors
|
|
*/
|
|
_dev_comp_vect_cpu_mask_clean_up(dd, entry);
|
|
unlock:
|
|
mutex_unlock(&node_affinity.lock);
|
|
dd->node = -1;
|
|
}
|
|
|
|
/*
|
|
* Function updates the irq affinity hint for msix after it has been changed
|
|
* by the user using the /proc/irq interface. This function only accepts
|
|
* one cpu in the mask.
|
|
*/
|
|
static void hfi1_update_sdma_affinity(struct hfi1_msix_entry *msix, int cpu)
|
|
{
|
|
struct sdma_engine *sde = msix->arg;
|
|
struct hfi1_devdata *dd = sde->dd;
|
|
struct hfi1_affinity_node *entry;
|
|
struct cpu_mask_set *set;
|
|
int i, old_cpu;
|
|
|
|
if (cpu > num_online_cpus() || cpu == sde->cpu)
|
|
return;
|
|
|
|
mutex_lock(&node_affinity.lock);
|
|
entry = node_affinity_lookup(dd->node);
|
|
if (!entry)
|
|
goto unlock;
|
|
|
|
old_cpu = sde->cpu;
|
|
sde->cpu = cpu;
|
|
cpumask_clear(&msix->mask);
|
|
cpumask_set_cpu(cpu, &msix->mask);
|
|
dd_dev_dbg(dd, "IRQ: %u, type %s engine %u -> cpu: %d\n",
|
|
msix->irq, irq_type_names[msix->type],
|
|
sde->this_idx, cpu);
|
|
irq_set_affinity_hint(msix->irq, &msix->mask);
|
|
|
|
/*
|
|
* Set the new cpu in the hfi1_affinity_node and clean
|
|
* the old cpu if it is not used by any other IRQ
|
|
*/
|
|
set = &entry->def_intr;
|
|
cpumask_set_cpu(cpu, &set->mask);
|
|
cpumask_set_cpu(cpu, &set->used);
|
|
for (i = 0; i < dd->num_msix_entries; i++) {
|
|
struct hfi1_msix_entry *other_msix;
|
|
|
|
other_msix = &dd->msix_entries[i];
|
|
if (other_msix->type != IRQ_SDMA || other_msix == msix)
|
|
continue;
|
|
|
|
if (cpumask_test_cpu(old_cpu, &other_msix->mask))
|
|
goto unlock;
|
|
}
|
|
cpumask_clear_cpu(old_cpu, &set->mask);
|
|
cpumask_clear_cpu(old_cpu, &set->used);
|
|
unlock:
|
|
mutex_unlock(&node_affinity.lock);
|
|
}
|
|
|
|
static void hfi1_irq_notifier_notify(struct irq_affinity_notify *notify,
|
|
const cpumask_t *mask)
|
|
{
|
|
int cpu = cpumask_first(mask);
|
|
struct hfi1_msix_entry *msix = container_of(notify,
|
|
struct hfi1_msix_entry,
|
|
notify);
|
|
|
|
/* Only one CPU configuration supported currently */
|
|
hfi1_update_sdma_affinity(msix, cpu);
|
|
}
|
|
|
|
static void hfi1_irq_notifier_release(struct kref *ref)
|
|
{
|
|
/*
|
|
* This is required by affinity notifier. We don't have anything to
|
|
* free here.
|
|
*/
|
|
}
|
|
|
|
static void hfi1_setup_sdma_notifier(struct hfi1_msix_entry *msix)
|
|
{
|
|
struct irq_affinity_notify *notify = &msix->notify;
|
|
|
|
notify->irq = msix->irq;
|
|
notify->notify = hfi1_irq_notifier_notify;
|
|
notify->release = hfi1_irq_notifier_release;
|
|
|
|
if (irq_set_affinity_notifier(notify->irq, notify))
|
|
pr_err("Failed to register sdma irq affinity notifier for irq %d\n",
|
|
notify->irq);
|
|
}
|
|
|
|
static void hfi1_cleanup_sdma_notifier(struct hfi1_msix_entry *msix)
|
|
{
|
|
struct irq_affinity_notify *notify = &msix->notify;
|
|
|
|
if (irq_set_affinity_notifier(notify->irq, NULL))
|
|
pr_err("Failed to cleanup sdma irq affinity notifier for irq %d\n",
|
|
notify->irq);
|
|
}
|
|
|
|
/*
|
|
* Function sets the irq affinity for msix.
|
|
* It *must* be called with node_affinity.lock held.
|
|
*/
|
|
static int get_irq_affinity(struct hfi1_devdata *dd,
|
|
struct hfi1_msix_entry *msix)
|
|
{
|
|
cpumask_var_t diff;
|
|
struct hfi1_affinity_node *entry;
|
|
struct cpu_mask_set *set = NULL;
|
|
struct sdma_engine *sde = NULL;
|
|
struct hfi1_ctxtdata *rcd = NULL;
|
|
char extra[64];
|
|
int cpu = -1;
|
|
|
|
extra[0] = '\0';
|
|
cpumask_clear(&msix->mask);
|
|
|
|
entry = node_affinity_lookup(dd->node);
|
|
|
|
switch (msix->type) {
|
|
case IRQ_SDMA:
|
|
sde = (struct sdma_engine *)msix->arg;
|
|
scnprintf(extra, 64, "engine %u", sde->this_idx);
|
|
set = &entry->def_intr;
|
|
break;
|
|
case IRQ_GENERAL:
|
|
cpu = cpumask_first(&entry->general_intr_mask);
|
|
break;
|
|
case IRQ_RCVCTXT:
|
|
rcd = (struct hfi1_ctxtdata *)msix->arg;
|
|
if (rcd->ctxt == HFI1_CTRL_CTXT)
|
|
cpu = cpumask_first(&entry->general_intr_mask);
|
|
else
|
|
set = &entry->rcv_intr;
|
|
scnprintf(extra, 64, "ctxt %u", rcd->ctxt);
|
|
break;
|
|
default:
|
|
dd_dev_err(dd, "Invalid IRQ type %d\n", msix->type);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* The general and control contexts are placed on a particular
|
|
* CPU, which is set above. Skip accounting for it. Everything else
|
|
* finds its CPU here.
|
|
*/
|
|
if (cpu == -1 && set) {
|
|
if (!zalloc_cpumask_var(&diff, GFP_KERNEL))
|
|
return -ENOMEM;
|
|
|
|
cpu = cpu_mask_set_get_first(set, diff);
|
|
if (cpu < 0) {
|
|
free_cpumask_var(diff);
|
|
dd_dev_err(dd, "Failure to obtain CPU for IRQ\n");
|
|
return cpu;
|
|
}
|
|
|
|
free_cpumask_var(diff);
|
|
}
|
|
|
|
cpumask_set_cpu(cpu, &msix->mask);
|
|
dd_dev_info(dd, "IRQ: %u, type %s %s -> cpu: %d\n",
|
|
msix->irq, irq_type_names[msix->type],
|
|
extra, cpu);
|
|
irq_set_affinity_hint(msix->irq, &msix->mask);
|
|
|
|
if (msix->type == IRQ_SDMA) {
|
|
sde->cpu = cpu;
|
|
hfi1_setup_sdma_notifier(msix);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int hfi1_get_irq_affinity(struct hfi1_devdata *dd, struct hfi1_msix_entry *msix)
|
|
{
|
|
int ret;
|
|
|
|
mutex_lock(&node_affinity.lock);
|
|
ret = get_irq_affinity(dd, msix);
|
|
mutex_unlock(&node_affinity.lock);
|
|
return ret;
|
|
}
|
|
|
|
void hfi1_put_irq_affinity(struct hfi1_devdata *dd,
|
|
struct hfi1_msix_entry *msix)
|
|
{
|
|
struct cpu_mask_set *set = NULL;
|
|
struct hfi1_ctxtdata *rcd;
|
|
struct hfi1_affinity_node *entry;
|
|
|
|
mutex_lock(&node_affinity.lock);
|
|
entry = node_affinity_lookup(dd->node);
|
|
|
|
switch (msix->type) {
|
|
case IRQ_SDMA:
|
|
set = &entry->def_intr;
|
|
hfi1_cleanup_sdma_notifier(msix);
|
|
break;
|
|
case IRQ_GENERAL:
|
|
/* Don't do accounting for general contexts */
|
|
break;
|
|
case IRQ_RCVCTXT:
|
|
rcd = (struct hfi1_ctxtdata *)msix->arg;
|
|
/* Don't do accounting for control contexts */
|
|
if (rcd->ctxt != HFI1_CTRL_CTXT)
|
|
set = &entry->rcv_intr;
|
|
break;
|
|
default:
|
|
mutex_unlock(&node_affinity.lock);
|
|
return;
|
|
}
|
|
|
|
if (set) {
|
|
cpumask_andnot(&set->used, &set->used, &msix->mask);
|
|
_cpu_mask_set_gen_dec(set);
|
|
}
|
|
|
|
irq_set_affinity_hint(msix->irq, NULL);
|
|
cpumask_clear(&msix->mask);
|
|
mutex_unlock(&node_affinity.lock);
|
|
}
|
|
|
|
/* This should be called with node_affinity.lock held */
|
|
static void find_hw_thread_mask(uint hw_thread_no, cpumask_var_t hw_thread_mask,
|
|
struct hfi1_affinity_node_list *affinity)
|
|
{
|
|
int possible, curr_cpu, i;
|
|
uint num_cores_per_socket = node_affinity.num_online_cpus /
|
|
affinity->num_core_siblings /
|
|
node_affinity.num_online_nodes;
|
|
|
|
cpumask_copy(hw_thread_mask, &affinity->proc.mask);
|
|
if (affinity->num_core_siblings > 0) {
|
|
/* Removing other siblings not needed for now */
|
|
possible = cpumask_weight(hw_thread_mask);
|
|
curr_cpu = cpumask_first(hw_thread_mask);
|
|
for (i = 0;
|
|
i < num_cores_per_socket * node_affinity.num_online_nodes;
|
|
i++)
|
|
curr_cpu = cpumask_next(curr_cpu, hw_thread_mask);
|
|
|
|
for (; i < possible; i++) {
|
|
cpumask_clear_cpu(curr_cpu, hw_thread_mask);
|
|
curr_cpu = cpumask_next(curr_cpu, hw_thread_mask);
|
|
}
|
|
|
|
/* Identifying correct HW threads within physical cores */
|
|
cpumask_shift_left(hw_thread_mask, hw_thread_mask,
|
|
num_cores_per_socket *
|
|
node_affinity.num_online_nodes *
|
|
hw_thread_no);
|
|
}
|
|
}
|
|
|
|
int hfi1_get_proc_affinity(int node)
|
|
{
|
|
int cpu = -1, ret, i;
|
|
struct hfi1_affinity_node *entry;
|
|
cpumask_var_t diff, hw_thread_mask, available_mask, intrs_mask;
|
|
const struct cpumask *node_mask,
|
|
*proc_mask = ¤t->cpus_allowed;
|
|
struct hfi1_affinity_node_list *affinity = &node_affinity;
|
|
struct cpu_mask_set *set = &affinity->proc;
|
|
|
|
/*
|
|
* check whether process/context affinity has already
|
|
* been set
|
|
*/
|
|
if (cpumask_weight(proc_mask) == 1) {
|
|
hfi1_cdbg(PROC, "PID %u %s affinity set to CPU %*pbl",
|
|
current->pid, current->comm,
|
|
cpumask_pr_args(proc_mask));
|
|
/*
|
|
* Mark the pre-set CPU as used. This is atomic so we don't
|
|
* need the lock
|
|
*/
|
|
cpu = cpumask_first(proc_mask);
|
|
cpumask_set_cpu(cpu, &set->used);
|
|
goto done;
|
|
} else if (cpumask_weight(proc_mask) < cpumask_weight(&set->mask)) {
|
|
hfi1_cdbg(PROC, "PID %u %s affinity set to CPU set(s) %*pbl",
|
|
current->pid, current->comm,
|
|
cpumask_pr_args(proc_mask));
|
|
goto done;
|
|
}
|
|
|
|
/*
|
|
* The process does not have a preset CPU affinity so find one to
|
|
* recommend using the following algorithm:
|
|
*
|
|
* For each user process that is opening a context on HFI Y:
|
|
* a) If all cores are filled, reinitialize the bitmask
|
|
* b) Fill real cores first, then HT cores (First set of HT
|
|
* cores on all physical cores, then second set of HT core,
|
|
* and, so on) in the following order:
|
|
*
|
|
* 1. Same NUMA node as HFI Y and not running an IRQ
|
|
* handler
|
|
* 2. Same NUMA node as HFI Y and running an IRQ handler
|
|
* 3. Different NUMA node to HFI Y and not running an IRQ
|
|
* handler
|
|
* 4. Different NUMA node to HFI Y and running an IRQ
|
|
* handler
|
|
* c) Mark core as filled in the bitmask. As user processes are
|
|
* done, clear cores from the bitmask.
|
|
*/
|
|
|
|
ret = zalloc_cpumask_var(&diff, GFP_KERNEL);
|
|
if (!ret)
|
|
goto done;
|
|
ret = zalloc_cpumask_var(&hw_thread_mask, GFP_KERNEL);
|
|
if (!ret)
|
|
goto free_diff;
|
|
ret = zalloc_cpumask_var(&available_mask, GFP_KERNEL);
|
|
if (!ret)
|
|
goto free_hw_thread_mask;
|
|
ret = zalloc_cpumask_var(&intrs_mask, GFP_KERNEL);
|
|
if (!ret)
|
|
goto free_available_mask;
|
|
|
|
mutex_lock(&affinity->lock);
|
|
/*
|
|
* If we've used all available HW threads, clear the mask and start
|
|
* overloading.
|
|
*/
|
|
_cpu_mask_set_gen_inc(set);
|
|
|
|
/*
|
|
* If NUMA node has CPUs used by interrupt handlers, include them in the
|
|
* interrupt handler mask.
|
|
*/
|
|
entry = node_affinity_lookup(node);
|
|
if (entry) {
|
|
cpumask_copy(intrs_mask, (entry->def_intr.gen ?
|
|
&entry->def_intr.mask :
|
|
&entry->def_intr.used));
|
|
cpumask_or(intrs_mask, intrs_mask, (entry->rcv_intr.gen ?
|
|
&entry->rcv_intr.mask :
|
|
&entry->rcv_intr.used));
|
|
cpumask_or(intrs_mask, intrs_mask, &entry->general_intr_mask);
|
|
}
|
|
hfi1_cdbg(PROC, "CPUs used by interrupts: %*pbl",
|
|
cpumask_pr_args(intrs_mask));
|
|
|
|
cpumask_copy(hw_thread_mask, &set->mask);
|
|
|
|
/*
|
|
* If HT cores are enabled, identify which HW threads within the
|
|
* physical cores should be used.
|
|
*/
|
|
if (affinity->num_core_siblings > 0) {
|
|
for (i = 0; i < affinity->num_core_siblings; i++) {
|
|
find_hw_thread_mask(i, hw_thread_mask, affinity);
|
|
|
|
/*
|
|
* If there's at least one available core for this HW
|
|
* thread number, stop looking for a core.
|
|
*
|
|
* diff will always be not empty at least once in this
|
|
* loop as the used mask gets reset when
|
|
* (set->mask == set->used) before this loop.
|
|
*/
|
|
cpumask_andnot(diff, hw_thread_mask, &set->used);
|
|
if (!cpumask_empty(diff))
|
|
break;
|
|
}
|
|
}
|
|
hfi1_cdbg(PROC, "Same available HW thread on all physical CPUs: %*pbl",
|
|
cpumask_pr_args(hw_thread_mask));
|
|
|
|
node_mask = cpumask_of_node(node);
|
|
hfi1_cdbg(PROC, "Device on NUMA %u, CPUs %*pbl", node,
|
|
cpumask_pr_args(node_mask));
|
|
|
|
/* Get cpumask of available CPUs on preferred NUMA */
|
|
cpumask_and(available_mask, hw_thread_mask, node_mask);
|
|
cpumask_andnot(available_mask, available_mask, &set->used);
|
|
hfi1_cdbg(PROC, "Available CPUs on NUMA %u: %*pbl", node,
|
|
cpumask_pr_args(available_mask));
|
|
|
|
/*
|
|
* At first, we don't want to place processes on the same
|
|
* CPUs as interrupt handlers. Then, CPUs running interrupt
|
|
* handlers are used.
|
|
*
|
|
* 1) If diff is not empty, then there are CPUs not running
|
|
* non-interrupt handlers available, so diff gets copied
|
|
* over to available_mask.
|
|
* 2) If diff is empty, then all CPUs not running interrupt
|
|
* handlers are taken, so available_mask contains all
|
|
* available CPUs running interrupt handlers.
|
|
* 3) If available_mask is empty, then all CPUs on the
|
|
* preferred NUMA node are taken, so other NUMA nodes are
|
|
* used for process assignments using the same method as
|
|
* the preferred NUMA node.
|
|
*/
|
|
cpumask_andnot(diff, available_mask, intrs_mask);
|
|
if (!cpumask_empty(diff))
|
|
cpumask_copy(available_mask, diff);
|
|
|
|
/* If we don't have CPUs on the preferred node, use other NUMA nodes */
|
|
if (cpumask_empty(available_mask)) {
|
|
cpumask_andnot(available_mask, hw_thread_mask, &set->used);
|
|
/* Excluding preferred NUMA cores */
|
|
cpumask_andnot(available_mask, available_mask, node_mask);
|
|
hfi1_cdbg(PROC,
|
|
"Preferred NUMA node cores are taken, cores available in other NUMA nodes: %*pbl",
|
|
cpumask_pr_args(available_mask));
|
|
|
|
/*
|
|
* At first, we don't want to place processes on the same
|
|
* CPUs as interrupt handlers.
|
|
*/
|
|
cpumask_andnot(diff, available_mask, intrs_mask);
|
|
if (!cpumask_empty(diff))
|
|
cpumask_copy(available_mask, diff);
|
|
}
|
|
hfi1_cdbg(PROC, "Possible CPUs for process: %*pbl",
|
|
cpumask_pr_args(available_mask));
|
|
|
|
cpu = cpumask_first(available_mask);
|
|
if (cpu >= nr_cpu_ids) /* empty */
|
|
cpu = -1;
|
|
else
|
|
cpumask_set_cpu(cpu, &set->used);
|
|
|
|
mutex_unlock(&affinity->lock);
|
|
hfi1_cdbg(PROC, "Process assigned to CPU %d", cpu);
|
|
|
|
free_cpumask_var(intrs_mask);
|
|
free_available_mask:
|
|
free_cpumask_var(available_mask);
|
|
free_hw_thread_mask:
|
|
free_cpumask_var(hw_thread_mask);
|
|
free_diff:
|
|
free_cpumask_var(diff);
|
|
done:
|
|
return cpu;
|
|
}
|
|
|
|
void hfi1_put_proc_affinity(int cpu)
|
|
{
|
|
struct hfi1_affinity_node_list *affinity = &node_affinity;
|
|
struct cpu_mask_set *set = &affinity->proc;
|
|
|
|
if (cpu < 0)
|
|
return;
|
|
|
|
mutex_lock(&affinity->lock);
|
|
cpu_mask_set_put(set, cpu);
|
|
hfi1_cdbg(PROC, "Returning CPU %d for future process assignment", cpu);
|
|
mutex_unlock(&affinity->lock);
|
|
}
|