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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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d8e704e461
All BCM7xxx integrated Gigabit PHYs have an issue in their MDIO management controller which will make the initial read or write to them to fail and return 0xffff. This is a real issue as the typical first thing we do is read from MII_PHYSID1 and MII_PHYSID2 from get_phy_id() to register a driver for these PHYs. Coupled with the workaround in drivers/net/phy/bcm7xxx.c, this workaround for the MDIO bus controller consists in scanning the list of PHYs to do this initial read workaround for as part of the MDIO bus reset routine which is invoked prior to mdiobus_scan(). Once we have a proper PHY driver/device registered, all workarounds are located there (e.g: power management suspend/resume calls). Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
262 lines
6.4 KiB
C
262 lines
6.4 KiB
C
/*
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* Broadcom UniMAC MDIO bus controller driver
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*
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* Copyright (C) 2014, Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/phy.h>
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/of_mdio.h>
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#define MDIO_CMD 0x00
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#define MDIO_START_BUSY (1 << 29)
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#define MDIO_READ_FAIL (1 << 28)
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#define MDIO_RD (2 << 26)
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#define MDIO_WR (1 << 26)
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#define MDIO_PMD_SHIFT 21
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#define MDIO_PMD_MASK 0x1F
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#define MDIO_REG_SHIFT 16
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#define MDIO_REG_MASK 0x1F
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#define MDIO_CFG 0x04
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#define MDIO_C22 (1 << 0)
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#define MDIO_C45 0
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#define MDIO_CLK_DIV_SHIFT 4
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#define MDIO_CLK_DIV_MASK 0x3F
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#define MDIO_SUPP_PREAMBLE (1 << 12)
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struct unimac_mdio_priv {
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struct mii_bus *mii_bus;
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void __iomem *base;
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};
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static inline void unimac_mdio_start(struct unimac_mdio_priv *priv)
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{
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u32 reg;
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reg = __raw_readl(priv->base + MDIO_CMD);
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reg |= MDIO_START_BUSY;
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__raw_writel(reg, priv->base + MDIO_CMD);
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}
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static inline unsigned int unimac_mdio_busy(struct unimac_mdio_priv *priv)
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{
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return __raw_readl(priv->base + MDIO_CMD) & MDIO_START_BUSY;
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}
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static int unimac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
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{
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struct unimac_mdio_priv *priv = bus->priv;
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unsigned int timeout = 1000;
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u32 cmd;
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/* Prepare the read operation */
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cmd = MDIO_RD | (phy_id << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT);
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__raw_writel(cmd, priv->base + MDIO_CMD);
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/* Start MDIO transaction */
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unimac_mdio_start(priv);
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do {
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if (!unimac_mdio_busy(priv))
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break;
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usleep_range(1000, 2000);
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} while (timeout--);
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if (!timeout)
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return -ETIMEDOUT;
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cmd = __raw_readl(priv->base + MDIO_CMD);
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/* Some broken devices are known not to release the line during
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* turn-around, e.g: Broadcom BCM53125 external switches, so check for
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* that condition here and ignore the MDIO controller read failure
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* indication.
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*/
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if (!(bus->phy_ignore_ta_mask & 1 << phy_id) && (cmd & MDIO_READ_FAIL))
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return -EIO;
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return cmd & 0xffff;
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}
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static int unimac_mdio_write(struct mii_bus *bus, int phy_id,
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int reg, u16 val)
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{
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struct unimac_mdio_priv *priv = bus->priv;
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unsigned int timeout = 1000;
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u32 cmd;
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/* Prepare the write operation */
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cmd = MDIO_WR | (phy_id << MDIO_PMD_SHIFT) |
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(reg << MDIO_REG_SHIFT) | (0xffff & val);
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__raw_writel(cmd, priv->base + MDIO_CMD);
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unimac_mdio_start(priv);
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do {
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if (!unimac_mdio_busy(priv))
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break;
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usleep_range(1000, 2000);
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} while (timeout--);
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if (!timeout)
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return -ETIMEDOUT;
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return 0;
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}
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/* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with
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* their internal MDIO management controller making them fail to successfully
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* be read from or written to for the first transaction. We insert a dummy
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* BMSR read here to make sure that phy_get_device() and get_phy_id() can
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* correctly read the PHY MII_PHYSID1/2 registers and successfully register a
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* PHY device for this peripheral.
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*
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* Once the PHY driver is registered, we can workaround subsequent reads from
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* there (e.g: during system-wide power management).
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*
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* bus->reset is invoked before mdiobus_scan during mdiobus_register and is
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* therefore the right location to stick that workaround. Since we do not want
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* to read from non-existing PHYs, we either use bus->phy_mask or do a manual
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* Device Tree scan to limit the search area.
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*/
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static int unimac_mdio_reset(struct mii_bus *bus)
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{
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struct device_node *np = bus->dev.of_node;
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struct device_node *child;
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u32 read_mask = 0;
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int addr;
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if (!np) {
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read_mask = ~bus->phy_mask;
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} else {
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for_each_available_child_of_node(np, child) {
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addr = of_mdio_parse_addr(&bus->dev, child);
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if (addr < 0)
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continue;
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read_mask |= 1 << addr;
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}
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}
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for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
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if (read_mask & 1 << addr)
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mdiobus_read(bus, addr, MII_BMSR);
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}
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return 0;
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}
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static int unimac_mdio_probe(struct platform_device *pdev)
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{
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struct unimac_mdio_priv *priv;
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struct device_node *np;
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struct mii_bus *bus;
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struct resource *r;
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int ret;
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np = pdev->dev.of_node;
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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/* Just ioremap, as this MDIO block is usually integrated into an
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* Ethernet MAC controller register range
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*/
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priv->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
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if (!priv->base) {
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dev_err(&pdev->dev, "failed to remap register\n");
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return -ENOMEM;
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}
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priv->mii_bus = mdiobus_alloc();
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if (!priv->mii_bus)
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return -ENOMEM;
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bus = priv->mii_bus;
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bus->priv = priv;
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bus->name = "unimac MII bus";
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bus->parent = &pdev->dev;
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bus->read = unimac_mdio_read;
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bus->write = unimac_mdio_write;
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bus->reset = unimac_mdio_reset;
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snprintf(bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
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bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
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if (!bus->irq) {
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ret = -ENOMEM;
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goto out_mdio_free;
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}
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ret = of_mdiobus_register(bus, np);
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if (ret) {
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dev_err(&pdev->dev, "MDIO bus registration failed\n");
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goto out_mdio_irq;
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}
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platform_set_drvdata(pdev, priv);
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dev_info(&pdev->dev, "Broadcom UniMAC MDIO bus at 0x%p\n", priv->base);
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return 0;
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out_mdio_irq:
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kfree(bus->irq);
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out_mdio_free:
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mdiobus_free(bus);
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return ret;
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}
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static int unimac_mdio_remove(struct platform_device *pdev)
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{
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struct unimac_mdio_priv *priv = platform_get_drvdata(pdev);
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mdiobus_unregister(priv->mii_bus);
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kfree(priv->mii_bus->irq);
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mdiobus_free(priv->mii_bus);
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return 0;
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}
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static const struct of_device_id unimac_mdio_ids[] = {
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{ .compatible = "brcm,genet-mdio-v4", },
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{ .compatible = "brcm,genet-mdio-v3", },
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{ .compatible = "brcm,genet-mdio-v2", },
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{ .compatible = "brcm,genet-mdio-v1", },
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{ .compatible = "brcm,unimac-mdio", },
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{ /* sentinel */ },
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};
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static struct platform_driver unimac_mdio_driver = {
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.driver = {
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.name = "unimac-mdio",
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.of_match_table = unimac_mdio_ids,
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},
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.probe = unimac_mdio_probe,
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.remove = unimac_mdio_remove,
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};
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module_platform_driver(unimac_mdio_driver);
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MODULE_AUTHOR("Broadcom Corporation");
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MODULE_DESCRIPTION("Broadcom UniMAC MDIO bus controller");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:unimac-mdio");
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