mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-29 23:36:45 +07:00
a36795c127
J-Type DPLLs have additional configuration parameters that need to be programmed when setting the multipler and divider for the DPLL. These parameters being the sigma delta divider (SD_DIV) for the DPLL and the digital controlled oscillator (DCO) to be used by the DPLL. The current code is implemented specifically to configure the OMAP3630 PER J-Type DPLL. The OMAP4430 USB DPLL is also a J-Type DPLL and so this code needs to be updated to work for both OMAP3 and OMAP4 devices and any other future devices that have J-TYPE DPLLs. For the OMAP3630 PER DPLL both the SD_DIV and DCO paramenters are used but for the OMAP4430 USB DPLL only the SD_DIV field is used. The current implementation will only program the SD_DIV and DCO fields if the DPLL has both and hence this does not work for OMAP4430. In order to make the code more generic add two new fields to the dpll_data structure for the SD_DIV field and DCO field bit-masks and only program these fields if the masks are defined for a specific DPLL. This simplifies the code and allows us to remove the flag DPLL_NO_DCO_SEL. Tested on OMAP36xx Zoom3 and OMAP4 Blaze. Signed-off-by: Jon Hunter <jon-hunter@ti.com> [paul@pwsan.com: removed explicit inlining and added '_' prefix on lookup_*() functions; added testing info to commit message; added 35xx comments back in] Signed-off-by: Paul Walmsley <paul@pwsan.com>
151 lines
4.8 KiB
C
151 lines
4.8 KiB
C
/*
|
|
* linux/arch/arm/mach-omap2/clock.h
|
|
*
|
|
* Copyright (C) 2005-2009 Texas Instruments, Inc.
|
|
* Copyright (C) 2004-2009 Nokia Corporation
|
|
*
|
|
* Contacts:
|
|
* Richard Woodruff <r-woodruff2@ti.com>
|
|
* Paul Walmsley
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
|
|
#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
|
|
|
|
#include <plat/clock.h>
|
|
|
|
/* The maximum error between a target DPLL rate and the rounded rate in Hz */
|
|
#define DEFAULT_DPLL_RATE_TOLERANCE 50000
|
|
|
|
/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
|
|
#define CORE_CLK_SRC_32K 0x0
|
|
#define CORE_CLK_SRC_DPLL 0x1
|
|
#define CORE_CLK_SRC_DPLL_X2 0x2
|
|
|
|
/* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
|
|
#define OMAP2XXX_EN_DPLL_LPBYPASS 0x1
|
|
#define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
|
|
#define OMAP2XXX_EN_DPLL_LOCKED 0x3
|
|
|
|
/* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
|
|
#define OMAP3XXX_EN_DPLL_LPBYPASS 0x5
|
|
#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
|
|
#define OMAP3XXX_EN_DPLL_LOCKED 0x7
|
|
|
|
/* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
|
|
#define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
|
|
#define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
|
|
#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
|
|
#define OMAP4XXX_EN_DPLL_LOCKED 0x7
|
|
|
|
/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
|
|
#define DPLL_LOW_POWER_STOP 0x1
|
|
#define DPLL_LOW_POWER_BYPASS 0x5
|
|
#define DPLL_LOCKED 0x7
|
|
|
|
/* DPLL Type and DCO Selection Flags */
|
|
#define DPLL_J_TYPE 0x1
|
|
|
|
int omap2_clk_enable(struct clk *clk);
|
|
void omap2_clk_disable(struct clk *clk);
|
|
long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
|
|
int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
|
|
int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
|
|
int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
|
|
long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
|
|
unsigned long omap3_dpll_recalc(struct clk *clk);
|
|
unsigned long omap3_clkoutx2_recalc(struct clk *clk);
|
|
void omap3_dpll_allow_idle(struct clk *clk);
|
|
void omap3_dpll_deny_idle(struct clk *clk);
|
|
u32 omap3_dpll_autoidle_read(struct clk *clk);
|
|
int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
|
|
int omap3_noncore_dpll_enable(struct clk *clk);
|
|
void omap3_noncore_dpll_disable(struct clk *clk);
|
|
|
|
#ifdef CONFIG_OMAP_RESET_CLOCKS
|
|
void omap2_clk_disable_unused(struct clk *clk);
|
|
#else
|
|
#define omap2_clk_disable_unused NULL
|
|
#endif
|
|
|
|
void omap2_init_clk_clkdm(struct clk *clk);
|
|
|
|
/* clkt_clksel.c public functions */
|
|
u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
|
|
u32 *new_div);
|
|
void omap2_init_clksel_parent(struct clk *clk);
|
|
unsigned long omap2_clksel_recalc(struct clk *clk);
|
|
long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
|
|
int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
|
|
int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
|
|
|
|
u32 omap2_get_dpll_rate(struct clk *clk);
|
|
void omap2_init_dpll_parent(struct clk *clk);
|
|
|
|
int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
|
|
|
|
|
|
#ifdef CONFIG_ARCH_OMAP2
|
|
void omap2xxx_clk_prepare_for_reboot(void);
|
|
#else
|
|
static inline void omap2xxx_clk_prepare_for_reboot(void)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP3
|
|
void omap3_clk_prepare_for_reboot(void);
|
|
#else
|
|
static inline void omap3_clk_prepare_for_reboot(void)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP4
|
|
void omap4_clk_prepare_for_reboot(void);
|
|
#else
|
|
static inline void omap4_clk_prepare_for_reboot(void)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
int omap2_dflt_clk_enable(struct clk *clk);
|
|
void omap2_dflt_clk_disable(struct clk *clk);
|
|
void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
|
|
u8 *other_bit);
|
|
void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
|
|
u8 *idlest_bit, u8 *idlest_val);
|
|
int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
|
|
void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
|
|
const char *core_ck_name,
|
|
const char *mpu_ck_name);
|
|
|
|
extern u8 cpu_mask;
|
|
|
|
extern const struct clkops clkops_omap2_dflt_wait;
|
|
extern const struct clkops clkops_dummy;
|
|
extern const struct clkops clkops_omap2_dflt;
|
|
|
|
extern struct clk_functions omap2_clk_functions;
|
|
extern struct clk *vclk, *sclk;
|
|
|
|
extern const struct clksel_rate gpt_32k_rates[];
|
|
extern const struct clksel_rate gpt_sys_rates[];
|
|
extern const struct clksel_rate gfx_l3_rates[];
|
|
|
|
#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_CPU_FREQ)
|
|
extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
|
|
extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
|
|
#else
|
|
#define omap2_clk_init_cpufreq_table 0
|
|
#define omap2_clk_exit_cpufreq_table 0
|
|
#endif
|
|
|
|
extern const struct clkops clkops_omap3_noncore_dpll_ops;
|
|
|
|
#endif
|