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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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58bff947e2
Not only when an IRQ's affinity equals cpu_online_mask is there no need to actually try to adjust the affinity, but also when it's a subset thereof. This particularly avoids adjustment attempts during system shutdown to any IRQs bound to CPU#0. Signed-off-by: Jan Beulich <jbeulich@novell.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Eric W. Biederman <ebiederm@xmission.com> Cc: Suresh Siddha <suresh.b.siddha@intel.com> Cc: Gary Hade <garyhade@us.ibm.com> LKML-Reference: <4D5D52C2020000780003272C@vpn.id2.novell.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
380 lines
9.4 KiB
C
380 lines
9.4 KiB
C
/*
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* Common interrupt code for 32 and 64 bit
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*/
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#include <linux/cpu.h>
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#include <linux/interrupt.h>
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#include <linux/kernel_stat.h>
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#include <linux/of.h>
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#include <linux/seq_file.h>
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#include <linux/smp.h>
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#include <linux/ftrace.h>
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#include <asm/apic.h>
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#include <asm/io_apic.h>
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#include <asm/irq.h>
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#include <asm/idle.h>
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#include <asm/mce.h>
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#include <asm/hw_irq.h>
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atomic_t irq_err_count;
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/* Function pointer for generic interrupt vector handling */
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void (*x86_platform_ipi_callback)(void) = NULL;
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/*
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* 'what should we do if we get a hw irq event on an illegal vector'.
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* each architecture has to answer this themselves.
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*/
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void ack_bad_irq(unsigned int irq)
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{
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if (printk_ratelimit())
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pr_err("unexpected IRQ trap at vector %02x\n", irq);
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/*
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* Currently unexpected vectors happen only on SMP and APIC.
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* We _must_ ack these because every local APIC has only N
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* irq slots per priority level, and a 'hanging, unacked' IRQ
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* holds up an irq slot - in excessive cases (when multiple
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* unexpected vectors occur) that might lock up the APIC
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* completely.
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* But only ack when the APIC is enabled -AK
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*/
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ack_APIC_irq();
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}
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#define irq_stats(x) (&per_cpu(irq_stat, x))
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/*
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* /proc/interrupts printing:
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*/
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static int show_other_interrupts(struct seq_file *p, int prec)
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{
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int j;
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seq_printf(p, "%*s: ", prec, "NMI");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
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seq_printf(p, " Non-maskable interrupts\n");
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#ifdef CONFIG_X86_LOCAL_APIC
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seq_printf(p, "%*s: ", prec, "LOC");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
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seq_printf(p, " Local timer interrupts\n");
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seq_printf(p, "%*s: ", prec, "SPU");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
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seq_printf(p, " Spurious interrupts\n");
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seq_printf(p, "%*s: ", prec, "PMI");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
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seq_printf(p, " Performance monitoring interrupts\n");
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seq_printf(p, "%*s: ", prec, "IWI");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
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seq_printf(p, " IRQ work interrupts\n");
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#endif
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if (x86_platform_ipi_callback) {
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seq_printf(p, "%*s: ", prec, "PLT");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
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seq_printf(p, " Platform interrupts\n");
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}
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#ifdef CONFIG_SMP
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seq_printf(p, "%*s: ", prec, "RES");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
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seq_printf(p, " Rescheduling interrupts\n");
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seq_printf(p, "%*s: ", prec, "CAL");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
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seq_printf(p, " Function call interrupts\n");
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seq_printf(p, "%*s: ", prec, "TLB");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
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seq_printf(p, " TLB shootdowns\n");
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#endif
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#ifdef CONFIG_X86_THERMAL_VECTOR
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seq_printf(p, "%*s: ", prec, "TRM");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
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seq_printf(p, " Thermal event interrupts\n");
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#endif
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#ifdef CONFIG_X86_MCE_THRESHOLD
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seq_printf(p, "%*s: ", prec, "THR");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
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seq_printf(p, " Threshold APIC interrupts\n");
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#endif
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#ifdef CONFIG_X86_MCE
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seq_printf(p, "%*s: ", prec, "MCE");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
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seq_printf(p, " Machine check exceptions\n");
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seq_printf(p, "%*s: ", prec, "MCP");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
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seq_printf(p, " Machine check polls\n");
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#endif
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seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
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#if defined(CONFIG_X86_IO_APIC)
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seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
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#endif
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return 0;
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}
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int show_interrupts(struct seq_file *p, void *v)
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{
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unsigned long flags, any_count = 0;
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int i = *(loff_t *) v, j, prec;
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struct irqaction *action;
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struct irq_desc *desc;
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if (i > nr_irqs)
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return 0;
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for (prec = 3, j = 1000; prec < 10 && j <= nr_irqs; ++prec)
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j *= 10;
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if (i == nr_irqs)
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return show_other_interrupts(p, prec);
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/* print header */
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if (i == 0) {
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seq_printf(p, "%*s", prec + 8, "");
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for_each_online_cpu(j)
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seq_printf(p, "CPU%-8d", j);
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seq_putc(p, '\n');
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}
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desc = irq_to_desc(i);
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if (!desc)
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return 0;
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raw_spin_lock_irqsave(&desc->lock, flags);
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for_each_online_cpu(j)
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any_count |= kstat_irqs_cpu(i, j);
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action = desc->action;
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if (!action && !any_count)
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goto out;
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seq_printf(p, "%*d: ", prec, i);
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
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seq_printf(p, " %8s", desc->irq_data.chip->name);
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seq_printf(p, "-%-8s", desc->name);
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if (action) {
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seq_printf(p, " %s", action->name);
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while ((action = action->next) != NULL)
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seq_printf(p, ", %s", action->name);
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}
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seq_putc(p, '\n');
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out:
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raw_spin_unlock_irqrestore(&desc->lock, flags);
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return 0;
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}
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/*
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* /proc/stat helpers
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*/
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u64 arch_irq_stat_cpu(unsigned int cpu)
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{
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u64 sum = irq_stats(cpu)->__nmi_count;
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#ifdef CONFIG_X86_LOCAL_APIC
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sum += irq_stats(cpu)->apic_timer_irqs;
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sum += irq_stats(cpu)->irq_spurious_count;
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sum += irq_stats(cpu)->apic_perf_irqs;
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sum += irq_stats(cpu)->apic_irq_work_irqs;
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#endif
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if (x86_platform_ipi_callback)
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sum += irq_stats(cpu)->x86_platform_ipis;
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#ifdef CONFIG_SMP
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sum += irq_stats(cpu)->irq_resched_count;
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sum += irq_stats(cpu)->irq_call_count;
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sum += irq_stats(cpu)->irq_tlb_count;
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#endif
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#ifdef CONFIG_X86_THERMAL_VECTOR
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sum += irq_stats(cpu)->irq_thermal_count;
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#endif
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#ifdef CONFIG_X86_MCE_THRESHOLD
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sum += irq_stats(cpu)->irq_threshold_count;
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#endif
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#ifdef CONFIG_X86_MCE
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sum += per_cpu(mce_exception_count, cpu);
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sum += per_cpu(mce_poll_count, cpu);
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#endif
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return sum;
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}
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u64 arch_irq_stat(void)
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{
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u64 sum = atomic_read(&irq_err_count);
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#ifdef CONFIG_X86_IO_APIC
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sum += atomic_read(&irq_mis_count);
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#endif
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return sum;
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}
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/*
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* do_IRQ handles all normal device IRQ's (the special
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* SMP cross-CPU interrupts have their own specific
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* handlers).
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*/
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unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
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{
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struct pt_regs *old_regs = set_irq_regs(regs);
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/* high bit used in ret_from_ code */
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unsigned vector = ~regs->orig_ax;
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unsigned irq;
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exit_idle();
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irq_enter();
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irq = __this_cpu_read(vector_irq[vector]);
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if (!handle_irq(irq, regs)) {
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ack_APIC_irq();
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if (printk_ratelimit())
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pr_emerg("%s: %d.%d No irq handler for vector (irq %d)\n",
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__func__, smp_processor_id(), vector, irq);
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}
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irq_exit();
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set_irq_regs(old_regs);
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return 1;
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}
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/*
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* Handler for X86_PLATFORM_IPI_VECTOR.
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*/
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void smp_x86_platform_ipi(struct pt_regs *regs)
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{
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struct pt_regs *old_regs = set_irq_regs(regs);
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ack_APIC_irq();
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exit_idle();
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irq_enter();
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inc_irq_stat(x86_platform_ipis);
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if (x86_platform_ipi_callback)
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x86_platform_ipi_callback();
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irq_exit();
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set_irq_regs(old_regs);
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}
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EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
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#ifdef CONFIG_OF
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unsigned int irq_create_of_mapping(struct device_node *controller,
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const u32 *intspec, unsigned int intsize)
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{
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return intspec[0];
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}
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EXPORT_SYMBOL_GPL(irq_create_of_mapping);
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#endif
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#ifdef CONFIG_HOTPLUG_CPU
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/* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
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void fixup_irqs(void)
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{
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unsigned int irq, vector;
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static int warned;
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struct irq_desc *desc;
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struct irq_data *data;
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for_each_irq_desc(irq, desc) {
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int break_affinity = 0;
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int set_affinity = 1;
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const struct cpumask *affinity;
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if (!desc)
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continue;
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if (irq == 2)
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continue;
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/* interrupt's are disabled at this point */
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raw_spin_lock(&desc->lock);
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data = &desc->irq_data;
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affinity = data->affinity;
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if (!irq_has_action(irq) ||
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cpumask_subset(affinity, cpu_online_mask)) {
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raw_spin_unlock(&desc->lock);
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continue;
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}
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/*
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* Complete the irq move. This cpu is going down and for
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* non intr-remapping case, we can't wait till this interrupt
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* arrives at this cpu before completing the irq move.
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*/
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irq_force_complete_move(irq);
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if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
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break_affinity = 1;
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affinity = cpu_all_mask;
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}
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if (!(desc->status & IRQ_MOVE_PCNTXT) && data->chip->irq_mask)
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data->chip->irq_mask(data);
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if (data->chip->irq_set_affinity)
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data->chip->irq_set_affinity(data, affinity, true);
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else if (!(warned++))
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set_affinity = 0;
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if (!(desc->status & IRQ_MOVE_PCNTXT) && data->chip->irq_unmask)
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data->chip->irq_unmask(data);
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raw_spin_unlock(&desc->lock);
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if (break_affinity && set_affinity)
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printk("Broke affinity for irq %i\n", irq);
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else if (!set_affinity)
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printk("Cannot set affinity for irq %i\n", irq);
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}
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/*
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* We can remove mdelay() and then send spuriuous interrupts to
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* new cpu targets for all the irqs that were handled previously by
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* this cpu. While it works, I have seen spurious interrupt messages
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* (nothing wrong but still...).
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*
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* So for now, retain mdelay(1) and check the IRR and then send those
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* interrupts to new targets as this cpu is already offlined...
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*/
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mdelay(1);
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for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
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unsigned int irr;
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if (__this_cpu_read(vector_irq[vector]) < 0)
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continue;
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irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
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if (irr & (1 << (vector % 32))) {
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irq = __this_cpu_read(vector_irq[vector]);
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desc = irq_to_desc(irq);
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data = &desc->irq_data;
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raw_spin_lock(&desc->lock);
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if (data->chip->irq_retrigger)
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data->chip->irq_retrigger(data);
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raw_spin_unlock(&desc->lock);
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}
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}
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}
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#endif
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