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143fefc8f3
Commit5f9f41c474
("MIPS: kernel: Prepare the JR instruction for emulation on MIPS R6") added support for emulating the JR instruction on MIPS R6 cores but that introduced a bug which could be triggered when hitting a JALR opcode because the code used the wrong field in the 'r_format' struct to determine the instruction opcode. This lead to crashes because an emulated JALR instruction was treated as a JR one when the R6 emulator was turned off. Fixes:5f9f41c474
("MIPS: kernel: Prepare the JR instruction for emulation on MIPS R6") Cc: <stable@vger.kernel.org> # 4.0+ Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10583/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2219 lines
54 KiB
C
2219 lines
54 KiB
C
/*
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* cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
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*
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* MIPS floating point support
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* Copyright (C) 1994-2000 Algorithmics Ltd.
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*
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* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc.
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* A complete emulator for MIPS coprocessor 1 instructions. This is
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* required for #float(switch) or #float(trap), where it catches all
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* COP1 instructions via the "CoProcessor Unusable" exception.
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*
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* More surprisingly it is also required for #float(ieee), to help out
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* the hardware FPU at the boundaries of the IEEE-754 representation
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* (denormalised values, infinities, underflow, etc). It is made
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* quite nasty because emulation of some non-COP1 instructions is
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* required, e.g. in branch delay slots.
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*
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* Note if you know that you won't have an FPU, then you'll get much
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* better performance by compiling with -msoft-float!
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*/
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#include <linux/sched.h>
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#include <linux/debugfs.h>
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#include <linux/kconfig.h>
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#include <linux/percpu-defs.h>
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#include <linux/perf_event.h>
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#include <asm/branch.h>
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#include <asm/inst.h>
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#include <asm/ptrace.h>
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#include <asm/signal.h>
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#include <asm/uaccess.h>
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#include <asm/cpu-info.h>
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#include <asm/processor.h>
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#include <asm/fpu_emulator.h>
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#include <asm/fpu.h>
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#include <asm/mips-r2-to-r6-emul.h>
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#include "ieee754.h"
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/* Function which emulates a floating point instruction. */
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static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
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mips_instruction);
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static int fpux_emu(struct pt_regs *,
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struct mips_fpu_struct *, mips_instruction, void *__user *);
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/* Control registers */
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#define FPCREG_RID 0 /* $0 = revision id */
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#define FPCREG_FCCR 25 /* $25 = fccr */
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#define FPCREG_FEXR 26 /* $26 = fexr */
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#define FPCREG_FENR 28 /* $28 = fenr */
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#define FPCREG_CSR 31 /* $31 = csr */
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/* convert condition code register number to csr bit */
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const unsigned int fpucondbit[8] = {
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FPU_CSR_COND,
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FPU_CSR_COND1,
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FPU_CSR_COND2,
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FPU_CSR_COND3,
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FPU_CSR_COND4,
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FPU_CSR_COND5,
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FPU_CSR_COND6,
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FPU_CSR_COND7
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};
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/* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
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static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
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static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
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static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
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static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
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/*
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* This functions translates a 32-bit microMIPS instruction
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* into a 32-bit MIPS32 instruction. Returns 0 on success
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* and SIGILL otherwise.
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*/
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static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
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{
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union mips_instruction insn = *insn_ptr;
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union mips_instruction mips32_insn = insn;
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int func, fmt, op;
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switch (insn.mm_i_format.opcode) {
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case mm_ldc132_op:
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mips32_insn.mm_i_format.opcode = ldc1_op;
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mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
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mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
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break;
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case mm_lwc132_op:
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mips32_insn.mm_i_format.opcode = lwc1_op;
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mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
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mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
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break;
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case mm_sdc132_op:
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mips32_insn.mm_i_format.opcode = sdc1_op;
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mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
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mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
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break;
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case mm_swc132_op:
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mips32_insn.mm_i_format.opcode = swc1_op;
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mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
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mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
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break;
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case mm_pool32i_op:
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/* NOTE: offset is << by 1 if in microMIPS mode. */
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if ((insn.mm_i_format.rt == mm_bc1f_op) ||
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(insn.mm_i_format.rt == mm_bc1t_op)) {
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mips32_insn.fb_format.opcode = cop1_op;
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mips32_insn.fb_format.bc = bc_op;
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mips32_insn.fb_format.flag =
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(insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
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} else
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return SIGILL;
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break;
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case mm_pool32f_op:
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switch (insn.mm_fp0_format.func) {
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case mm_32f_01_op:
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case mm_32f_11_op:
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case mm_32f_02_op:
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case mm_32f_12_op:
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case mm_32f_41_op:
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case mm_32f_51_op:
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case mm_32f_42_op:
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case mm_32f_52_op:
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op = insn.mm_fp0_format.func;
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if (op == mm_32f_01_op)
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func = madd_s_op;
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else if (op == mm_32f_11_op)
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func = madd_d_op;
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else if (op == mm_32f_02_op)
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func = nmadd_s_op;
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else if (op == mm_32f_12_op)
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func = nmadd_d_op;
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else if (op == mm_32f_41_op)
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func = msub_s_op;
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else if (op == mm_32f_51_op)
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func = msub_d_op;
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else if (op == mm_32f_42_op)
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func = nmsub_s_op;
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else
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func = nmsub_d_op;
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mips32_insn.fp6_format.opcode = cop1x_op;
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mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
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mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
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mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
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mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
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mips32_insn.fp6_format.func = func;
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break;
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case mm_32f_10_op:
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func = -1; /* Invalid */
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op = insn.mm_fp5_format.op & 0x7;
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if (op == mm_ldxc1_op)
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func = ldxc1_op;
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else if (op == mm_sdxc1_op)
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func = sdxc1_op;
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else if (op == mm_lwxc1_op)
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func = lwxc1_op;
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else if (op == mm_swxc1_op)
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func = swxc1_op;
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if (func != -1) {
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mips32_insn.r_format.opcode = cop1x_op;
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mips32_insn.r_format.rs =
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insn.mm_fp5_format.base;
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mips32_insn.r_format.rt =
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insn.mm_fp5_format.index;
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mips32_insn.r_format.rd = 0;
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mips32_insn.r_format.re = insn.mm_fp5_format.fd;
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mips32_insn.r_format.func = func;
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} else
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return SIGILL;
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break;
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case mm_32f_40_op:
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op = -1; /* Invalid */
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if (insn.mm_fp2_format.op == mm_fmovt_op)
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op = 1;
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else if (insn.mm_fp2_format.op == mm_fmovf_op)
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op = 0;
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if (op != -1) {
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mips32_insn.fp0_format.opcode = cop1_op;
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mips32_insn.fp0_format.fmt =
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sdps_format[insn.mm_fp2_format.fmt];
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mips32_insn.fp0_format.ft =
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(insn.mm_fp2_format.cc<<2) + op;
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mips32_insn.fp0_format.fs =
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insn.mm_fp2_format.fs;
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mips32_insn.fp0_format.fd =
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insn.mm_fp2_format.fd;
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mips32_insn.fp0_format.func = fmovc_op;
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} else
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return SIGILL;
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break;
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case mm_32f_60_op:
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func = -1; /* Invalid */
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if (insn.mm_fp0_format.op == mm_fadd_op)
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func = fadd_op;
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else if (insn.mm_fp0_format.op == mm_fsub_op)
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func = fsub_op;
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else if (insn.mm_fp0_format.op == mm_fmul_op)
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func = fmul_op;
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else if (insn.mm_fp0_format.op == mm_fdiv_op)
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func = fdiv_op;
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if (func != -1) {
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mips32_insn.fp0_format.opcode = cop1_op;
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mips32_insn.fp0_format.fmt =
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sdps_format[insn.mm_fp0_format.fmt];
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mips32_insn.fp0_format.ft =
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insn.mm_fp0_format.ft;
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mips32_insn.fp0_format.fs =
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insn.mm_fp0_format.fs;
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mips32_insn.fp0_format.fd =
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insn.mm_fp0_format.fd;
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mips32_insn.fp0_format.func = func;
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} else
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return SIGILL;
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break;
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case mm_32f_70_op:
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func = -1; /* Invalid */
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if (insn.mm_fp0_format.op == mm_fmovn_op)
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func = fmovn_op;
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else if (insn.mm_fp0_format.op == mm_fmovz_op)
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func = fmovz_op;
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if (func != -1) {
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mips32_insn.fp0_format.opcode = cop1_op;
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mips32_insn.fp0_format.fmt =
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sdps_format[insn.mm_fp0_format.fmt];
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mips32_insn.fp0_format.ft =
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insn.mm_fp0_format.ft;
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mips32_insn.fp0_format.fs =
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insn.mm_fp0_format.fs;
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mips32_insn.fp0_format.fd =
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insn.mm_fp0_format.fd;
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mips32_insn.fp0_format.func = func;
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} else
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return SIGILL;
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break;
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case mm_32f_73_op: /* POOL32FXF */
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switch (insn.mm_fp1_format.op) {
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case mm_movf0_op:
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case mm_movf1_op:
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case mm_movt0_op:
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case mm_movt1_op:
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if ((insn.mm_fp1_format.op & 0x7f) ==
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mm_movf0_op)
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op = 0;
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else
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op = 1;
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mips32_insn.r_format.opcode = spec_op;
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mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
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mips32_insn.r_format.rt =
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(insn.mm_fp4_format.cc << 2) + op;
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mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
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mips32_insn.r_format.re = 0;
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mips32_insn.r_format.func = movc_op;
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break;
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case mm_fcvtd0_op:
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case mm_fcvtd1_op:
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case mm_fcvts0_op:
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case mm_fcvts1_op:
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if ((insn.mm_fp1_format.op & 0x7f) ==
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mm_fcvtd0_op) {
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func = fcvtd_op;
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fmt = swl_format[insn.mm_fp3_format.fmt];
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} else {
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func = fcvts_op;
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fmt = dwl_format[insn.mm_fp3_format.fmt];
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}
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mips32_insn.fp0_format.opcode = cop1_op;
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mips32_insn.fp0_format.fmt = fmt;
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mips32_insn.fp0_format.ft = 0;
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mips32_insn.fp0_format.fs =
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insn.mm_fp3_format.fs;
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mips32_insn.fp0_format.fd =
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insn.mm_fp3_format.rt;
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mips32_insn.fp0_format.func = func;
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break;
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case mm_fmov0_op:
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case mm_fmov1_op:
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case mm_fabs0_op:
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case mm_fabs1_op:
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case mm_fneg0_op:
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case mm_fneg1_op:
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if ((insn.mm_fp1_format.op & 0x7f) ==
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mm_fmov0_op)
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func = fmov_op;
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else if ((insn.mm_fp1_format.op & 0x7f) ==
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mm_fabs0_op)
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func = fabs_op;
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else
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func = fneg_op;
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mips32_insn.fp0_format.opcode = cop1_op;
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mips32_insn.fp0_format.fmt =
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sdps_format[insn.mm_fp3_format.fmt];
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mips32_insn.fp0_format.ft = 0;
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mips32_insn.fp0_format.fs =
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insn.mm_fp3_format.fs;
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mips32_insn.fp0_format.fd =
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insn.mm_fp3_format.rt;
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mips32_insn.fp0_format.func = func;
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break;
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case mm_ffloorl_op:
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case mm_ffloorw_op:
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case mm_fceill_op:
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case mm_fceilw_op:
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case mm_ftruncl_op:
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case mm_ftruncw_op:
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case mm_froundl_op:
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case mm_froundw_op:
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case mm_fcvtl_op:
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case mm_fcvtw_op:
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if (insn.mm_fp1_format.op == mm_ffloorl_op)
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func = ffloorl_op;
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else if (insn.mm_fp1_format.op == mm_ffloorw_op)
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func = ffloor_op;
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else if (insn.mm_fp1_format.op == mm_fceill_op)
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func = fceill_op;
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else if (insn.mm_fp1_format.op == mm_fceilw_op)
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func = fceil_op;
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else if (insn.mm_fp1_format.op == mm_ftruncl_op)
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func = ftruncl_op;
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else if (insn.mm_fp1_format.op == mm_ftruncw_op)
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func = ftrunc_op;
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else if (insn.mm_fp1_format.op == mm_froundl_op)
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func = froundl_op;
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else if (insn.mm_fp1_format.op == mm_froundw_op)
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func = fround_op;
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else if (insn.mm_fp1_format.op == mm_fcvtl_op)
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func = fcvtl_op;
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else
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func = fcvtw_op;
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mips32_insn.fp0_format.opcode = cop1_op;
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mips32_insn.fp0_format.fmt =
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sd_format[insn.mm_fp1_format.fmt];
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mips32_insn.fp0_format.ft = 0;
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mips32_insn.fp0_format.fs =
|
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insn.mm_fp1_format.fs;
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mips32_insn.fp0_format.fd =
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insn.mm_fp1_format.rt;
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mips32_insn.fp0_format.func = func;
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break;
|
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case mm_frsqrt_op:
|
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case mm_fsqrt_op:
|
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case mm_frecip_op:
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if (insn.mm_fp1_format.op == mm_frsqrt_op)
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func = frsqrt_op;
|
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else if (insn.mm_fp1_format.op == mm_fsqrt_op)
|
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func = fsqrt_op;
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else
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func = frecip_op;
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mips32_insn.fp0_format.opcode = cop1_op;
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mips32_insn.fp0_format.fmt =
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sdps_format[insn.mm_fp1_format.fmt];
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mips32_insn.fp0_format.ft = 0;
|
|
mips32_insn.fp0_format.fs =
|
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insn.mm_fp1_format.fs;
|
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mips32_insn.fp0_format.fd =
|
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insn.mm_fp1_format.rt;
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mips32_insn.fp0_format.func = func;
|
|
break;
|
|
case mm_mfc1_op:
|
|
case mm_mtc1_op:
|
|
case mm_cfc1_op:
|
|
case mm_ctc1_op:
|
|
case mm_mfhc1_op:
|
|
case mm_mthc1_op:
|
|
if (insn.mm_fp1_format.op == mm_mfc1_op)
|
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op = mfc_op;
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|
else if (insn.mm_fp1_format.op == mm_mtc1_op)
|
|
op = mtc_op;
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|
else if (insn.mm_fp1_format.op == mm_cfc1_op)
|
|
op = cfc_op;
|
|
else if (insn.mm_fp1_format.op == mm_ctc1_op)
|
|
op = ctc_op;
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|
else if (insn.mm_fp1_format.op == mm_mfhc1_op)
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op = mfhc_op;
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else
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op = mthc_op;
|
|
mips32_insn.fp1_format.opcode = cop1_op;
|
|
mips32_insn.fp1_format.op = op;
|
|
mips32_insn.fp1_format.rt =
|
|
insn.mm_fp1_format.rt;
|
|
mips32_insn.fp1_format.fs =
|
|
insn.mm_fp1_format.fs;
|
|
mips32_insn.fp1_format.fd = 0;
|
|
mips32_insn.fp1_format.func = 0;
|
|
break;
|
|
default:
|
|
return SIGILL;
|
|
}
|
|
break;
|
|
case mm_32f_74_op: /* c.cond.fmt */
|
|
mips32_insn.fp0_format.opcode = cop1_op;
|
|
mips32_insn.fp0_format.fmt =
|
|
sdps_format[insn.mm_fp4_format.fmt];
|
|
mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
|
|
mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
|
|
mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
|
|
mips32_insn.fp0_format.func =
|
|
insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
|
|
break;
|
|
default:
|
|
return SIGILL;
|
|
}
|
|
break;
|
|
default:
|
|
return SIGILL;
|
|
}
|
|
|
|
*insn_ptr = mips32_insn;
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Redundant with logic already in kernel/branch.c,
|
|
* embedded in compute_return_epc. At some point,
|
|
* a single subroutine should be used across both
|
|
* modules.
|
|
*/
|
|
static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
|
|
unsigned long *contpc)
|
|
{
|
|
union mips_instruction insn = (union mips_instruction)dec_insn.insn;
|
|
unsigned int fcr31;
|
|
unsigned int bit = 0;
|
|
|
|
switch (insn.i_format.opcode) {
|
|
case spec_op:
|
|
switch (insn.r_format.func) {
|
|
case jalr_op:
|
|
regs->regs[insn.r_format.rd] =
|
|
regs->cp0_epc + dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
/* Fall through */
|
|
case jr_op:
|
|
/* For R6, JR already emulated in jalr_op */
|
|
if (NO_R6EMU && insn.r_format.func == jr_op)
|
|
break;
|
|
*contpc = regs->regs[insn.r_format.rs];
|
|
return 1;
|
|
}
|
|
break;
|
|
case bcond_op:
|
|
switch (insn.i_format.rt) {
|
|
case bltzal_op:
|
|
case bltzall_op:
|
|
if (NO_R6EMU && (insn.i_format.rs ||
|
|
insn.i_format.rt == bltzall_op))
|
|
break;
|
|
|
|
regs->regs[31] = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
/* Fall through */
|
|
case bltzl_op:
|
|
if (NO_R6EMU)
|
|
break;
|
|
case bltz_op:
|
|
if ((long)regs->regs[insn.i_format.rs] < 0)
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
(insn.i_format.simmediate << 2);
|
|
else
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
return 1;
|
|
case bgezal_op:
|
|
case bgezall_op:
|
|
if (NO_R6EMU && (insn.i_format.rs ||
|
|
insn.i_format.rt == bgezall_op))
|
|
break;
|
|
|
|
regs->regs[31] = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
/* Fall through */
|
|
case bgezl_op:
|
|
if (NO_R6EMU)
|
|
break;
|
|
case bgez_op:
|
|
if ((long)regs->regs[insn.i_format.rs] >= 0)
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
(insn.i_format.simmediate << 2);
|
|
else
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
return 1;
|
|
}
|
|
break;
|
|
case jalx_op:
|
|
set_isa16_mode(bit);
|
|
case jal_op:
|
|
regs->regs[31] = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
/* Fall through */
|
|
case j_op:
|
|
*contpc = regs->cp0_epc + dec_insn.pc_inc;
|
|
*contpc >>= 28;
|
|
*contpc <<= 28;
|
|
*contpc |= (insn.j_format.target << 2);
|
|
/* Set microMIPS mode bit: XOR for jalx. */
|
|
*contpc ^= bit;
|
|
return 1;
|
|
case beql_op:
|
|
if (NO_R6EMU)
|
|
break;
|
|
case beq_op:
|
|
if (regs->regs[insn.i_format.rs] ==
|
|
regs->regs[insn.i_format.rt])
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
(insn.i_format.simmediate << 2);
|
|
else
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
return 1;
|
|
case bnel_op:
|
|
if (NO_R6EMU)
|
|
break;
|
|
case bne_op:
|
|
if (regs->regs[insn.i_format.rs] !=
|
|
regs->regs[insn.i_format.rt])
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
(insn.i_format.simmediate << 2);
|
|
else
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
return 1;
|
|
case blezl_op:
|
|
if (!insn.i_format.rt && NO_R6EMU)
|
|
break;
|
|
case blez_op:
|
|
|
|
/*
|
|
* Compact branches for R6 for the
|
|
* blez and blezl opcodes.
|
|
* BLEZ | rs = 0 | rt != 0 == BLEZALC
|
|
* BLEZ | rs = rt != 0 == BGEZALC
|
|
* BLEZ | rs != 0 | rt != 0 == BGEUC
|
|
* BLEZL | rs = 0 | rt != 0 == BLEZC
|
|
* BLEZL | rs = rt != 0 == BGEZC
|
|
* BLEZL | rs != 0 | rt != 0 == BGEC
|
|
*
|
|
* For real BLEZ{,L}, rt is always 0.
|
|
*/
|
|
if (cpu_has_mips_r6 && insn.i_format.rt) {
|
|
if ((insn.i_format.opcode == blez_op) &&
|
|
((!insn.i_format.rs && insn.i_format.rt) ||
|
|
(insn.i_format.rs == insn.i_format.rt)))
|
|
regs->regs[31] = regs->cp0_epc +
|
|
dec_insn.pc_inc;
|
|
*contpc = regs->cp0_epc + dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
|
|
return 1;
|
|
}
|
|
if ((long)regs->regs[insn.i_format.rs] <= 0)
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
(insn.i_format.simmediate << 2);
|
|
else
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
return 1;
|
|
case bgtzl_op:
|
|
if (!insn.i_format.rt && NO_R6EMU)
|
|
break;
|
|
case bgtz_op:
|
|
/*
|
|
* Compact branches for R6 for the
|
|
* bgtz and bgtzl opcodes.
|
|
* BGTZ | rs = 0 | rt != 0 == BGTZALC
|
|
* BGTZ | rs = rt != 0 == BLTZALC
|
|
* BGTZ | rs != 0 | rt != 0 == BLTUC
|
|
* BGTZL | rs = 0 | rt != 0 == BGTZC
|
|
* BGTZL | rs = rt != 0 == BLTZC
|
|
* BGTZL | rs != 0 | rt != 0 == BLTC
|
|
*
|
|
* *ZALC varint for BGTZ &&& rt != 0
|
|
* For real GTZ{,L}, rt is always 0.
|
|
*/
|
|
if (cpu_has_mips_r6 && insn.i_format.rt) {
|
|
if ((insn.i_format.opcode == blez_op) &&
|
|
((!insn.i_format.rs && insn.i_format.rt) ||
|
|
(insn.i_format.rs == insn.i_format.rt)))
|
|
regs->regs[31] = regs->cp0_epc +
|
|
dec_insn.pc_inc;
|
|
*contpc = regs->cp0_epc + dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
|
|
return 1;
|
|
}
|
|
|
|
if ((long)regs->regs[insn.i_format.rs] > 0)
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
(insn.i_format.simmediate << 2);
|
|
else
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
return 1;
|
|
case cbcond0_op:
|
|
case cbcond1_op:
|
|
if (!cpu_has_mips_r6)
|
|
break;
|
|
if (insn.i_format.rt && !insn.i_format.rs)
|
|
regs->regs[31] = regs->cp0_epc + 4;
|
|
*contpc = regs->cp0_epc + dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
|
|
return 1;
|
|
#ifdef CONFIG_CPU_CAVIUM_OCTEON
|
|
case lwc2_op: /* This is bbit0 on Octeon */
|
|
if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
|
|
*contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
|
|
else
|
|
*contpc = regs->cp0_epc + 8;
|
|
return 1;
|
|
case ldc2_op: /* This is bbit032 on Octeon */
|
|
if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
|
|
*contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
|
|
else
|
|
*contpc = regs->cp0_epc + 8;
|
|
return 1;
|
|
case swc2_op: /* This is bbit1 on Octeon */
|
|
if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
|
|
*contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
|
|
else
|
|
*contpc = regs->cp0_epc + 8;
|
|
return 1;
|
|
case sdc2_op: /* This is bbit132 on Octeon */
|
|
if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
|
|
*contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
|
|
else
|
|
*contpc = regs->cp0_epc + 8;
|
|
return 1;
|
|
#else
|
|
case bc6_op:
|
|
/*
|
|
* Only valid for MIPS R6 but we can still end up
|
|
* here from a broken userland so just tell emulator
|
|
* this is not a branch and let it break later on.
|
|
*/
|
|
if (!cpu_has_mips_r6)
|
|
break;
|
|
*contpc = regs->cp0_epc + dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
|
|
return 1;
|
|
case balc6_op:
|
|
if (!cpu_has_mips_r6)
|
|
break;
|
|
regs->regs[31] = regs->cp0_epc + 4;
|
|
*contpc = regs->cp0_epc + dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
|
|
return 1;
|
|
case beqzcjic_op:
|
|
if (!cpu_has_mips_r6)
|
|
break;
|
|
*contpc = regs->cp0_epc + dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
|
|
return 1;
|
|
case bnezcjialc_op:
|
|
if (!cpu_has_mips_r6)
|
|
break;
|
|
if (!insn.i_format.rs)
|
|
regs->regs[31] = regs->cp0_epc + 4;
|
|
*contpc = regs->cp0_epc + dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
|
|
return 1;
|
|
#endif
|
|
case cop0_op:
|
|
case cop1_op:
|
|
/* Need to check for R6 bc1nez and bc1eqz branches */
|
|
if (cpu_has_mips_r6 &&
|
|
((insn.i_format.rs == bc1eqz_op) ||
|
|
(insn.i_format.rs == bc1nez_op))) {
|
|
bit = 0;
|
|
switch (insn.i_format.rs) {
|
|
case bc1eqz_op:
|
|
if (get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)
|
|
bit = 1;
|
|
break;
|
|
case bc1nez_op:
|
|
if (!(get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1))
|
|
bit = 1;
|
|
break;
|
|
}
|
|
if (bit)
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
(insn.i_format.simmediate << 2);
|
|
else
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
|
|
return 1;
|
|
}
|
|
/* R2/R6 compatible cop1 instruction. Fall through */
|
|
case cop2_op:
|
|
case cop1x_op:
|
|
if (insn.i_format.rs == bc_op) {
|
|
preempt_disable();
|
|
if (is_fpu_owner())
|
|
fcr31 = read_32bit_cp1_register(CP1_STATUS);
|
|
else
|
|
fcr31 = current->thread.fpu.fcr31;
|
|
preempt_enable();
|
|
|
|
bit = (insn.i_format.rt >> 2);
|
|
bit += (bit != 0);
|
|
bit += 23;
|
|
switch (insn.i_format.rt & 3) {
|
|
case 0: /* bc1f */
|
|
case 2: /* bc1fl */
|
|
if (~fcr31 & (1 << bit))
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
(insn.i_format.simmediate << 2);
|
|
else
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
return 1;
|
|
case 1: /* bc1t */
|
|
case 3: /* bc1tl */
|
|
if (fcr31 & (1 << bit))
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
(insn.i_format.simmediate << 2);
|
|
else
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
return 1;
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* In the Linux kernel, we support selection of FPR format on the
|
|
* basis of the Status.FR bit. If an FPU is not present, the FR bit
|
|
* is hardwired to zero, which would imply a 32-bit FPU even for
|
|
* 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
|
|
* FPU emu is slow and bulky and optimizing this function offers fairly
|
|
* sizeable benefits so we try to be clever and make this function return
|
|
* a constant whenever possible, that is on 64-bit kernels without O32
|
|
* compatibility enabled and on 32-bit without 64-bit FPU support.
|
|
*/
|
|
static inline int cop1_64bit(struct pt_regs *xcp)
|
|
{
|
|
if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
|
|
return 1;
|
|
else if (config_enabled(CONFIG_32BIT) &&
|
|
!config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
|
|
return 0;
|
|
|
|
return !test_thread_flag(TIF_32BIT_FPREGS);
|
|
}
|
|
|
|
static inline bool hybrid_fprs(void)
|
|
{
|
|
return test_thread_flag(TIF_HYBRID_FPREGS);
|
|
}
|
|
|
|
#define SIFROMREG(si, x) \
|
|
do { \
|
|
if (cop1_64bit(xcp) && !hybrid_fprs()) \
|
|
(si) = (int)get_fpr32(&ctx->fpr[x], 0); \
|
|
else \
|
|
(si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
|
|
} while (0)
|
|
|
|
#define SITOREG(si, x) \
|
|
do { \
|
|
if (cop1_64bit(xcp) && !hybrid_fprs()) { \
|
|
unsigned i; \
|
|
set_fpr32(&ctx->fpr[x], 0, si); \
|
|
for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
|
|
set_fpr32(&ctx->fpr[x], i, 0); \
|
|
} else { \
|
|
set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
|
|
} \
|
|
} while (0)
|
|
|
|
#define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
|
|
|
|
#define SITOHREG(si, x) \
|
|
do { \
|
|
unsigned i; \
|
|
set_fpr32(&ctx->fpr[x], 1, si); \
|
|
for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
|
|
set_fpr32(&ctx->fpr[x], i, 0); \
|
|
} while (0)
|
|
|
|
#define DIFROMREG(di, x) \
|
|
((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
|
|
|
|
#define DITOREG(di, x) \
|
|
do { \
|
|
unsigned fpr, i; \
|
|
fpr = (x) & ~(cop1_64bit(xcp) == 0); \
|
|
set_fpr64(&ctx->fpr[fpr], 0, di); \
|
|
for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
|
|
set_fpr64(&ctx->fpr[fpr], i, 0); \
|
|
} while (0)
|
|
|
|
#define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
|
|
#define SPTOREG(sp, x) SITOREG((sp).bits, x)
|
|
#define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
|
|
#define DPTOREG(dp, x) DITOREG((dp).bits, x)
|
|
|
|
/*
|
|
* Emulate a CFC1 instruction.
|
|
*/
|
|
static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
|
mips_instruction ir)
|
|
{
|
|
u32 fcr31 = ctx->fcr31;
|
|
u32 value = 0;
|
|
|
|
switch (MIPSInst_RD(ir)) {
|
|
case FPCREG_CSR:
|
|
value = fcr31;
|
|
pr_debug("%p gpr[%d]<-csr=%08x\n",
|
|
(void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
|
|
break;
|
|
|
|
case FPCREG_FENR:
|
|
if (!cpu_has_mips_r)
|
|
break;
|
|
value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
|
|
MIPS_FENR_FS;
|
|
value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM);
|
|
pr_debug("%p gpr[%d]<-enr=%08x\n",
|
|
(void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
|
|
break;
|
|
|
|
case FPCREG_FEXR:
|
|
if (!cpu_has_mips_r)
|
|
break;
|
|
value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
|
|
pr_debug("%p gpr[%d]<-exr=%08x\n",
|
|
(void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
|
|
break;
|
|
|
|
case FPCREG_FCCR:
|
|
if (!cpu_has_mips_r)
|
|
break;
|
|
value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
|
|
MIPS_FCCR_COND0;
|
|
value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
|
|
(MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0);
|
|
pr_debug("%p gpr[%d]<-ccr=%08x\n",
|
|
(void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
|
|
break;
|
|
|
|
case FPCREG_RID:
|
|
value = boot_cpu_data.fpu_id;
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if (MIPSInst_RT(ir))
|
|
xcp->regs[MIPSInst_RT(ir)] = value;
|
|
}
|
|
|
|
/*
|
|
* Emulate a CTC1 instruction.
|
|
*/
|
|
static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
|
mips_instruction ir)
|
|
{
|
|
u32 fcr31 = ctx->fcr31;
|
|
u32 value;
|
|
u32 mask;
|
|
|
|
if (MIPSInst_RT(ir) == 0)
|
|
value = 0;
|
|
else
|
|
value = xcp->regs[MIPSInst_RT(ir)];
|
|
|
|
switch (MIPSInst_RD(ir)) {
|
|
case FPCREG_CSR:
|
|
pr_debug("%p gpr[%d]->csr=%08x\n",
|
|
(void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
|
|
|
|
/* Preserve read-only bits. */
|
|
mask = boot_cpu_data.fpu_msk31;
|
|
fcr31 = (value & ~mask) | (fcr31 & mask);
|
|
break;
|
|
|
|
case FPCREG_FENR:
|
|
if (!cpu_has_mips_r)
|
|
break;
|
|
pr_debug("%p gpr[%d]->enr=%08x\n",
|
|
(void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
|
|
fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM);
|
|
fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
|
|
FPU_CSR_FS;
|
|
fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM);
|
|
break;
|
|
|
|
case FPCREG_FEXR:
|
|
if (!cpu_has_mips_r)
|
|
break;
|
|
pr_debug("%p gpr[%d]->exr=%08x\n",
|
|
(void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
|
|
fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S);
|
|
fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
|
|
break;
|
|
|
|
case FPCREG_FCCR:
|
|
if (!cpu_has_mips_r)
|
|
break;
|
|
pr_debug("%p gpr[%d]->ccr=%08x\n",
|
|
(void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
|
|
fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND);
|
|
fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
|
|
FPU_CSR_COND;
|
|
fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
|
|
FPU_CSR_CONDX;
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
ctx->fcr31 = fcr31;
|
|
}
|
|
|
|
/*
|
|
* Emulate the single floating point instruction pointed at by EPC.
|
|
* Two instructions if the instruction is in a branch delay slot.
|
|
*/
|
|
|
|
static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
|
struct mm_decoded_insn dec_insn, void *__user *fault_addr)
|
|
{
|
|
unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
|
|
unsigned int cond, cbit;
|
|
mips_instruction ir;
|
|
int likely, pc_inc;
|
|
u32 __user *wva;
|
|
u64 __user *dva;
|
|
u32 wval;
|
|
u64 dval;
|
|
int sig;
|
|
|
|
/*
|
|
* These are giving gcc a gentle hint about what to expect in
|
|
* dec_inst in order to do better optimization.
|
|
*/
|
|
if (!cpu_has_mmips && dec_insn.micro_mips_mode)
|
|
unreachable();
|
|
|
|
/* XXX NEC Vr54xx bug workaround */
|
|
if (delay_slot(xcp)) {
|
|
if (dec_insn.micro_mips_mode) {
|
|
if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
|
|
clear_delay_slot(xcp);
|
|
} else {
|
|
if (!isBranchInstr(xcp, dec_insn, &contpc))
|
|
clear_delay_slot(xcp);
|
|
}
|
|
}
|
|
|
|
if (delay_slot(xcp)) {
|
|
/*
|
|
* The instruction to be emulated is in a branch delay slot
|
|
* which means that we have to emulate the branch instruction
|
|
* BEFORE we do the cop1 instruction.
|
|
*
|
|
* This branch could be a COP1 branch, but in that case we
|
|
* would have had a trap for that instruction, and would not
|
|
* come through this route.
|
|
*
|
|
* Linux MIPS branch emulator operates on context, updating the
|
|
* cp0_epc.
|
|
*/
|
|
ir = dec_insn.next_insn; /* process delay slot instr */
|
|
pc_inc = dec_insn.next_pc_inc;
|
|
} else {
|
|
ir = dec_insn.insn; /* process current instr */
|
|
pc_inc = dec_insn.pc_inc;
|
|
}
|
|
|
|
/*
|
|
* Since microMIPS FPU instructios are a subset of MIPS32 FPU
|
|
* instructions, we want to convert microMIPS FPU instructions
|
|
* into MIPS32 instructions so that we could reuse all of the
|
|
* FPU emulation code.
|
|
*
|
|
* NOTE: We cannot do this for branch instructions since they
|
|
* are not a subset. Example: Cannot emulate a 16-bit
|
|
* aligned target address with a MIPS32 instruction.
|
|
*/
|
|
if (dec_insn.micro_mips_mode) {
|
|
/*
|
|
* If next instruction is a 16-bit instruction, then it
|
|
* it cannot be a FPU instruction. This could happen
|
|
* since we can be called for non-FPU instructions.
|
|
*/
|
|
if ((pc_inc == 2) ||
|
|
(microMIPS32_to_MIPS32((union mips_instruction *)&ir)
|
|
== SIGILL))
|
|
return SIGILL;
|
|
}
|
|
|
|
emul:
|
|
perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
|
|
MIPS_FPU_EMU_INC_STATS(emulated);
|
|
switch (MIPSInst_OPCODE(ir)) {
|
|
case ldc1_op:
|
|
dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
|
|
MIPSInst_SIMM(ir));
|
|
MIPS_FPU_EMU_INC_STATS(loads);
|
|
|
|
if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = dva;
|
|
return SIGBUS;
|
|
}
|
|
if (__get_user(dval, dva)) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = dva;
|
|
return SIGSEGV;
|
|
}
|
|
DITOREG(dval, MIPSInst_RT(ir));
|
|
break;
|
|
|
|
case sdc1_op:
|
|
dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
|
|
MIPSInst_SIMM(ir));
|
|
MIPS_FPU_EMU_INC_STATS(stores);
|
|
DIFROMREG(dval, MIPSInst_RT(ir));
|
|
if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = dva;
|
|
return SIGBUS;
|
|
}
|
|
if (__put_user(dval, dva)) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = dva;
|
|
return SIGSEGV;
|
|
}
|
|
break;
|
|
|
|
case lwc1_op:
|
|
wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
|
|
MIPSInst_SIMM(ir));
|
|
MIPS_FPU_EMU_INC_STATS(loads);
|
|
if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = wva;
|
|
return SIGBUS;
|
|
}
|
|
if (__get_user(wval, wva)) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = wva;
|
|
return SIGSEGV;
|
|
}
|
|
SITOREG(wval, MIPSInst_RT(ir));
|
|
break;
|
|
|
|
case swc1_op:
|
|
wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
|
|
MIPSInst_SIMM(ir));
|
|
MIPS_FPU_EMU_INC_STATS(stores);
|
|
SIFROMREG(wval, MIPSInst_RT(ir));
|
|
if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = wva;
|
|
return SIGBUS;
|
|
}
|
|
if (__put_user(wval, wva)) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = wva;
|
|
return SIGSEGV;
|
|
}
|
|
break;
|
|
|
|
case cop1_op:
|
|
switch (MIPSInst_RS(ir)) {
|
|
case dmfc_op:
|
|
if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
|
|
return SIGILL;
|
|
|
|
/* copregister fs -> gpr[rt] */
|
|
if (MIPSInst_RT(ir) != 0) {
|
|
DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
|
|
MIPSInst_RD(ir));
|
|
}
|
|
break;
|
|
|
|
case dmtc_op:
|
|
if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
|
|
return SIGILL;
|
|
|
|
/* copregister fs <- rt */
|
|
DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
|
|
break;
|
|
|
|
case mfhc_op:
|
|
if (!cpu_has_mips_r2)
|
|
goto sigill;
|
|
|
|
/* copregister rd -> gpr[rt] */
|
|
if (MIPSInst_RT(ir) != 0) {
|
|
SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
|
|
MIPSInst_RD(ir));
|
|
}
|
|
break;
|
|
|
|
case mthc_op:
|
|
if (!cpu_has_mips_r2)
|
|
goto sigill;
|
|
|
|
/* copregister rd <- gpr[rt] */
|
|
SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
|
|
break;
|
|
|
|
case mfc_op:
|
|
/* copregister rd -> gpr[rt] */
|
|
if (MIPSInst_RT(ir) != 0) {
|
|
SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
|
|
MIPSInst_RD(ir));
|
|
}
|
|
break;
|
|
|
|
case mtc_op:
|
|
/* copregister rd <- rt */
|
|
SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
|
|
break;
|
|
|
|
case cfc_op:
|
|
/* cop control register rd -> gpr[rt] */
|
|
cop1_cfc(xcp, ctx, ir);
|
|
break;
|
|
|
|
case ctc_op:
|
|
/* copregister rd <- rt */
|
|
cop1_ctc(xcp, ctx, ir);
|
|
if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
|
|
return SIGFPE;
|
|
}
|
|
break;
|
|
|
|
case bc_op:
|
|
if (delay_slot(xcp))
|
|
return SIGILL;
|
|
|
|
if (cpu_has_mips_4_5_r)
|
|
cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
|
|
else
|
|
cbit = FPU_CSR_COND;
|
|
cond = ctx->fcr31 & cbit;
|
|
|
|
likely = 0;
|
|
switch (MIPSInst_RT(ir) & 3) {
|
|
case bcfl_op:
|
|
if (cpu_has_mips_2_3_4_5_r)
|
|
likely = 1;
|
|
/* Fall through */
|
|
case bcf_op:
|
|
cond = !cond;
|
|
break;
|
|
case bctl_op:
|
|
if (cpu_has_mips_2_3_4_5_r)
|
|
likely = 1;
|
|
/* Fall through */
|
|
case bct_op:
|
|
break;
|
|
}
|
|
|
|
set_delay_slot(xcp);
|
|
if (cond) {
|
|
/*
|
|
* Branch taken: emulate dslot instruction
|
|
*/
|
|
unsigned long bcpc;
|
|
|
|
/*
|
|
* Remember EPC at the branch to point back
|
|
* at so that any delay-slot instruction
|
|
* signal is not silently ignored.
|
|
*/
|
|
bcpc = xcp->cp0_epc;
|
|
xcp->cp0_epc += dec_insn.pc_inc;
|
|
|
|
contpc = MIPSInst_SIMM(ir);
|
|
ir = dec_insn.next_insn;
|
|
if (dec_insn.micro_mips_mode) {
|
|
contpc = (xcp->cp0_epc + (contpc << 1));
|
|
|
|
/* If 16-bit instruction, not FPU. */
|
|
if ((dec_insn.next_pc_inc == 2) ||
|
|
(microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
|
|
|
|
/*
|
|
* Since this instruction will
|
|
* be put on the stack with
|
|
* 32-bit words, get around
|
|
* this problem by putting a
|
|
* NOP16 as the second one.
|
|
*/
|
|
if (dec_insn.next_pc_inc == 2)
|
|
ir = (ir & (~0xffff)) | MM_NOP16;
|
|
|
|
/*
|
|
* Single step the non-CP1
|
|
* instruction in the dslot.
|
|
*/
|
|
sig = mips_dsemul(xcp, ir,
|
|
contpc);
|
|
if (sig)
|
|
xcp->cp0_epc = bcpc;
|
|
/*
|
|
* SIGILL forces out of
|
|
* the emulation loop.
|
|
*/
|
|
return sig ? sig : SIGILL;
|
|
}
|
|
} else
|
|
contpc = (xcp->cp0_epc + (contpc << 2));
|
|
|
|
switch (MIPSInst_OPCODE(ir)) {
|
|
case lwc1_op:
|
|
case swc1_op:
|
|
goto emul;
|
|
|
|
case ldc1_op:
|
|
case sdc1_op:
|
|
if (cpu_has_mips_2_3_4_5_r)
|
|
goto emul;
|
|
|
|
goto bc_sigill;
|
|
|
|
case cop1_op:
|
|
goto emul;
|
|
|
|
case cop1x_op:
|
|
if (cpu_has_mips_4_5_64_r2_r6)
|
|
/* its one of ours */
|
|
goto emul;
|
|
|
|
goto bc_sigill;
|
|
|
|
case spec_op:
|
|
switch (MIPSInst_FUNC(ir)) {
|
|
case movc_op:
|
|
if (cpu_has_mips_4_5_r)
|
|
goto emul;
|
|
|
|
goto bc_sigill;
|
|
}
|
|
break;
|
|
|
|
bc_sigill:
|
|
xcp->cp0_epc = bcpc;
|
|
return SIGILL;
|
|
}
|
|
|
|
/*
|
|
* Single step the non-cp1
|
|
* instruction in the dslot
|
|
*/
|
|
sig = mips_dsemul(xcp, ir, contpc);
|
|
if (sig)
|
|
xcp->cp0_epc = bcpc;
|
|
/* SIGILL forces out of the emulation loop. */
|
|
return sig ? sig : SIGILL;
|
|
} else if (likely) { /* branch not taken */
|
|
/*
|
|
* branch likely nullifies
|
|
* dslot if not taken
|
|
*/
|
|
xcp->cp0_epc += dec_insn.pc_inc;
|
|
contpc += dec_insn.pc_inc;
|
|
/*
|
|
* else continue & execute
|
|
* dslot as normal insn
|
|
*/
|
|
}
|
|
break;
|
|
|
|
default:
|
|
if (!(MIPSInst_RS(ir) & 0x10))
|
|
return SIGILL;
|
|
|
|
/* a real fpu computation instruction */
|
|
if ((sig = fpu_emu(xcp, ctx, ir)))
|
|
return sig;
|
|
}
|
|
break;
|
|
|
|
case cop1x_op:
|
|
if (!cpu_has_mips_4_5_64_r2_r6)
|
|
return SIGILL;
|
|
|
|
sig = fpux_emu(xcp, ctx, ir, fault_addr);
|
|
if (sig)
|
|
return sig;
|
|
break;
|
|
|
|
case spec_op:
|
|
if (!cpu_has_mips_4_5_r)
|
|
return SIGILL;
|
|
|
|
if (MIPSInst_FUNC(ir) != movc_op)
|
|
return SIGILL;
|
|
cond = fpucondbit[MIPSInst_RT(ir) >> 2];
|
|
if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
|
|
xcp->regs[MIPSInst_RD(ir)] =
|
|
xcp->regs[MIPSInst_RS(ir)];
|
|
break;
|
|
default:
|
|
sigill:
|
|
return SIGILL;
|
|
}
|
|
|
|
/* we did it !! */
|
|
xcp->cp0_epc = contpc;
|
|
clear_delay_slot(xcp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Conversion table from MIPS compare ops 48-63
|
|
* cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
|
|
*/
|
|
static const unsigned char cmptab[8] = {
|
|
0, /* cmp_0 (sig) cmp_sf */
|
|
IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
|
|
IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
|
|
IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
|
|
IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
|
|
IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
|
|
IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
|
|
IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
|
|
};
|
|
|
|
|
|
/*
|
|
* Additional MIPS4 instructions
|
|
*/
|
|
|
|
#define DEF3OP(name, p, f1, f2, f3) \
|
|
static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
|
|
union ieee754##p s, union ieee754##p t) \
|
|
{ \
|
|
struct _ieee754_csr ieee754_csr_save; \
|
|
s = f1(s, t); \
|
|
ieee754_csr_save = ieee754_csr; \
|
|
s = f2(s, r); \
|
|
ieee754_csr_save.cx |= ieee754_csr.cx; \
|
|
ieee754_csr_save.sx |= ieee754_csr.sx; \
|
|
s = f3(s); \
|
|
ieee754_csr.cx |= ieee754_csr_save.cx; \
|
|
ieee754_csr.sx |= ieee754_csr_save.sx; \
|
|
return s; \
|
|
}
|
|
|
|
static union ieee754dp fpemu_dp_recip(union ieee754dp d)
|
|
{
|
|
return ieee754dp_div(ieee754dp_one(0), d);
|
|
}
|
|
|
|
static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
|
|
{
|
|
return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
|
|
}
|
|
|
|
static union ieee754sp fpemu_sp_recip(union ieee754sp s)
|
|
{
|
|
return ieee754sp_div(ieee754sp_one(0), s);
|
|
}
|
|
|
|
static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
|
|
{
|
|
return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
|
|
}
|
|
|
|
DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
|
|
DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
|
|
DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
|
|
DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
|
|
DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
|
|
DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
|
|
DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
|
|
DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
|
|
|
|
static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
|
mips_instruction ir, void *__user *fault_addr)
|
|
{
|
|
unsigned rcsr = 0; /* resulting csr */
|
|
|
|
MIPS_FPU_EMU_INC_STATS(cp1xops);
|
|
|
|
switch (MIPSInst_FMA_FFMT(ir)) {
|
|
case s_fmt:{ /* 0 */
|
|
|
|
union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
|
|
union ieee754sp fd, fr, fs, ft;
|
|
u32 __user *va;
|
|
u32 val;
|
|
|
|
switch (MIPSInst_FUNC(ir)) {
|
|
case lwxc1_op:
|
|
va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
|
|
xcp->regs[MIPSInst_FT(ir)]);
|
|
|
|
MIPS_FPU_EMU_INC_STATS(loads);
|
|
if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = va;
|
|
return SIGBUS;
|
|
}
|
|
if (__get_user(val, va)) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = va;
|
|
return SIGSEGV;
|
|
}
|
|
SITOREG(val, MIPSInst_FD(ir));
|
|
break;
|
|
|
|
case swxc1_op:
|
|
va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
|
|
xcp->regs[MIPSInst_FT(ir)]);
|
|
|
|
MIPS_FPU_EMU_INC_STATS(stores);
|
|
|
|
SIFROMREG(val, MIPSInst_FS(ir));
|
|
if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = va;
|
|
return SIGBUS;
|
|
}
|
|
if (put_user(val, va)) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = va;
|
|
return SIGSEGV;
|
|
}
|
|
break;
|
|
|
|
case madd_s_op:
|
|
handler = fpemu_sp_madd;
|
|
goto scoptop;
|
|
case msub_s_op:
|
|
handler = fpemu_sp_msub;
|
|
goto scoptop;
|
|
case nmadd_s_op:
|
|
handler = fpemu_sp_nmadd;
|
|
goto scoptop;
|
|
case nmsub_s_op:
|
|
handler = fpemu_sp_nmsub;
|
|
goto scoptop;
|
|
|
|
scoptop:
|
|
SPFROMREG(fr, MIPSInst_FR(ir));
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
SPFROMREG(ft, MIPSInst_FT(ir));
|
|
fd = (*handler) (fr, fs, ft);
|
|
SPTOREG(fd, MIPSInst_FD(ir));
|
|
|
|
copcsr:
|
|
if (ieee754_cxtest(IEEE754_INEXACT)) {
|
|
MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
|
|
rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
|
|
}
|
|
if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
|
|
MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
|
|
rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
|
|
}
|
|
if (ieee754_cxtest(IEEE754_OVERFLOW)) {
|
|
MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
|
|
rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
|
|
}
|
|
if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
|
|
MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
|
|
rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
|
|
}
|
|
|
|
ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
|
|
if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
|
|
/*printk ("SIGFPE: FPU csr = %08x\n",
|
|
ctx->fcr31); */
|
|
return SIGFPE;
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
return SIGILL;
|
|
}
|
|
break;
|
|
}
|
|
|
|
case d_fmt:{ /* 1 */
|
|
union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
|
|
union ieee754dp fd, fr, fs, ft;
|
|
u64 __user *va;
|
|
u64 val;
|
|
|
|
switch (MIPSInst_FUNC(ir)) {
|
|
case ldxc1_op:
|
|
va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
|
|
xcp->regs[MIPSInst_FT(ir)]);
|
|
|
|
MIPS_FPU_EMU_INC_STATS(loads);
|
|
if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = va;
|
|
return SIGBUS;
|
|
}
|
|
if (__get_user(val, va)) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = va;
|
|
return SIGSEGV;
|
|
}
|
|
DITOREG(val, MIPSInst_FD(ir));
|
|
break;
|
|
|
|
case sdxc1_op:
|
|
va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
|
|
xcp->regs[MIPSInst_FT(ir)]);
|
|
|
|
MIPS_FPU_EMU_INC_STATS(stores);
|
|
DIFROMREG(val, MIPSInst_FS(ir));
|
|
if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = va;
|
|
return SIGBUS;
|
|
}
|
|
if (__put_user(val, va)) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = va;
|
|
return SIGSEGV;
|
|
}
|
|
break;
|
|
|
|
case madd_d_op:
|
|
handler = fpemu_dp_madd;
|
|
goto dcoptop;
|
|
case msub_d_op:
|
|
handler = fpemu_dp_msub;
|
|
goto dcoptop;
|
|
case nmadd_d_op:
|
|
handler = fpemu_dp_nmadd;
|
|
goto dcoptop;
|
|
case nmsub_d_op:
|
|
handler = fpemu_dp_nmsub;
|
|
goto dcoptop;
|
|
|
|
dcoptop:
|
|
DPFROMREG(fr, MIPSInst_FR(ir));
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
DPFROMREG(ft, MIPSInst_FT(ir));
|
|
fd = (*handler) (fr, fs, ft);
|
|
DPTOREG(fd, MIPSInst_FD(ir));
|
|
goto copcsr;
|
|
|
|
default:
|
|
return SIGILL;
|
|
}
|
|
break;
|
|
}
|
|
|
|
case 0x3:
|
|
if (MIPSInst_FUNC(ir) != pfetch_op)
|
|
return SIGILL;
|
|
|
|
/* ignore prefx operation */
|
|
break;
|
|
|
|
default:
|
|
return SIGILL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
* Emulate a single COP1 arithmetic instruction.
|
|
*/
|
|
static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
|
mips_instruction ir)
|
|
{
|
|
int rfmt; /* resulting format */
|
|
unsigned rcsr = 0; /* resulting csr */
|
|
unsigned int oldrm;
|
|
unsigned int cbit;
|
|
unsigned cond;
|
|
union {
|
|
union ieee754dp d;
|
|
union ieee754sp s;
|
|
int w;
|
|
s64 l;
|
|
} rv; /* resulting value */
|
|
u64 bits;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(cp1ops);
|
|
switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
|
|
case s_fmt: { /* 0 */
|
|
union {
|
|
union ieee754sp(*b) (union ieee754sp, union ieee754sp);
|
|
union ieee754sp(*u) (union ieee754sp);
|
|
} handler;
|
|
union ieee754sp fs, ft;
|
|
|
|
switch (MIPSInst_FUNC(ir)) {
|
|
/* binary ops */
|
|
case fadd_op:
|
|
handler.b = ieee754sp_add;
|
|
goto scopbop;
|
|
case fsub_op:
|
|
handler.b = ieee754sp_sub;
|
|
goto scopbop;
|
|
case fmul_op:
|
|
handler.b = ieee754sp_mul;
|
|
goto scopbop;
|
|
case fdiv_op:
|
|
handler.b = ieee754sp_div;
|
|
goto scopbop;
|
|
|
|
/* unary ops */
|
|
case fsqrt_op:
|
|
if (!cpu_has_mips_2_3_4_5_r)
|
|
return SIGILL;
|
|
|
|
handler.u = ieee754sp_sqrt;
|
|
goto scopuop;
|
|
|
|
/*
|
|
* Note that on some MIPS IV implementations such as the
|
|
* R5000 and R8000 the FSQRT and FRECIP instructions do not
|
|
* achieve full IEEE-754 accuracy - however this emulator does.
|
|
*/
|
|
case frsqrt_op:
|
|
if (!cpu_has_mips_4_5_64_r2_r6)
|
|
return SIGILL;
|
|
|
|
handler.u = fpemu_sp_rsqrt;
|
|
goto scopuop;
|
|
|
|
case frecip_op:
|
|
if (!cpu_has_mips_4_5_64_r2_r6)
|
|
return SIGILL;
|
|
|
|
handler.u = fpemu_sp_recip;
|
|
goto scopuop;
|
|
|
|
case fmovc_op:
|
|
if (!cpu_has_mips_4_5_r)
|
|
return SIGILL;
|
|
|
|
cond = fpucondbit[MIPSInst_FT(ir) >> 2];
|
|
if (((ctx->fcr31 & cond) != 0) !=
|
|
((MIPSInst_FT(ir) & 1) != 0))
|
|
return 0;
|
|
SPFROMREG(rv.s, MIPSInst_FS(ir));
|
|
break;
|
|
|
|
case fmovz_op:
|
|
if (!cpu_has_mips_4_5_r)
|
|
return SIGILL;
|
|
|
|
if (xcp->regs[MIPSInst_FT(ir)] != 0)
|
|
return 0;
|
|
SPFROMREG(rv.s, MIPSInst_FS(ir));
|
|
break;
|
|
|
|
case fmovn_op:
|
|
if (!cpu_has_mips_4_5_r)
|
|
return SIGILL;
|
|
|
|
if (xcp->regs[MIPSInst_FT(ir)] == 0)
|
|
return 0;
|
|
SPFROMREG(rv.s, MIPSInst_FS(ir));
|
|
break;
|
|
|
|
case fabs_op:
|
|
handler.u = ieee754sp_abs;
|
|
goto scopuop;
|
|
|
|
case fneg_op:
|
|
handler.u = ieee754sp_neg;
|
|
goto scopuop;
|
|
|
|
case fmov_op:
|
|
/* an easy one */
|
|
SPFROMREG(rv.s, MIPSInst_FS(ir));
|
|
goto copcsr;
|
|
|
|
/* binary op on handler */
|
|
scopbop:
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
SPFROMREG(ft, MIPSInst_FT(ir));
|
|
|
|
rv.s = (*handler.b) (fs, ft);
|
|
goto copcsr;
|
|
scopuop:
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.s = (*handler.u) (fs);
|
|
goto copcsr;
|
|
copcsr:
|
|
if (ieee754_cxtest(IEEE754_INEXACT)) {
|
|
MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
|
|
rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
|
|
}
|
|
if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
|
|
MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
|
|
rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
|
|
}
|
|
if (ieee754_cxtest(IEEE754_OVERFLOW)) {
|
|
MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
|
|
rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
|
|
}
|
|
if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
|
|
MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
|
|
rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
|
|
}
|
|
if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
|
|
MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
|
|
rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
|
|
}
|
|
break;
|
|
|
|
/* unary conv ops */
|
|
case fcvts_op:
|
|
return SIGILL; /* not defined */
|
|
|
|
case fcvtd_op:
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.d = ieee754dp_fsp(fs);
|
|
rfmt = d_fmt;
|
|
goto copcsr;
|
|
|
|
case fcvtw_op:
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.w = ieee754sp_tint(fs);
|
|
rfmt = w_fmt;
|
|
goto copcsr;
|
|
|
|
case fround_op:
|
|
case ftrunc_op:
|
|
case fceil_op:
|
|
case ffloor_op:
|
|
if (!cpu_has_mips_2_3_4_5_r)
|
|
return SIGILL;
|
|
|
|
oldrm = ieee754_csr.rm;
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
ieee754_csr.rm = MIPSInst_FUNC(ir);
|
|
rv.w = ieee754sp_tint(fs);
|
|
ieee754_csr.rm = oldrm;
|
|
rfmt = w_fmt;
|
|
goto copcsr;
|
|
|
|
case fcvtl_op:
|
|
if (!cpu_has_mips_3_4_5_64_r2_r6)
|
|
return SIGILL;
|
|
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.l = ieee754sp_tlong(fs);
|
|
rfmt = l_fmt;
|
|
goto copcsr;
|
|
|
|
case froundl_op:
|
|
case ftruncl_op:
|
|
case fceill_op:
|
|
case ffloorl_op:
|
|
if (!cpu_has_mips_3_4_5_64_r2_r6)
|
|
return SIGILL;
|
|
|
|
oldrm = ieee754_csr.rm;
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
ieee754_csr.rm = MIPSInst_FUNC(ir);
|
|
rv.l = ieee754sp_tlong(fs);
|
|
ieee754_csr.rm = oldrm;
|
|
rfmt = l_fmt;
|
|
goto copcsr;
|
|
|
|
default:
|
|
if (MIPSInst_FUNC(ir) >= fcmp_op) {
|
|
unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
|
|
union ieee754sp fs, ft;
|
|
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
SPFROMREG(ft, MIPSInst_FT(ir));
|
|
rv.w = ieee754sp_cmp(fs, ft,
|
|
cmptab[cmpop & 0x7], cmpop & 0x8);
|
|
rfmt = -1;
|
|
if ((cmpop & 0x8) && ieee754_cxtest
|
|
(IEEE754_INVALID_OPERATION))
|
|
rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
|
|
else
|
|
goto copcsr;
|
|
|
|
} else
|
|
return SIGILL;
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
|
|
case d_fmt: {
|
|
union ieee754dp fs, ft;
|
|
union {
|
|
union ieee754dp(*b) (union ieee754dp, union ieee754dp);
|
|
union ieee754dp(*u) (union ieee754dp);
|
|
} handler;
|
|
|
|
switch (MIPSInst_FUNC(ir)) {
|
|
/* binary ops */
|
|
case fadd_op:
|
|
handler.b = ieee754dp_add;
|
|
goto dcopbop;
|
|
case fsub_op:
|
|
handler.b = ieee754dp_sub;
|
|
goto dcopbop;
|
|
case fmul_op:
|
|
handler.b = ieee754dp_mul;
|
|
goto dcopbop;
|
|
case fdiv_op:
|
|
handler.b = ieee754dp_div;
|
|
goto dcopbop;
|
|
|
|
/* unary ops */
|
|
case fsqrt_op:
|
|
if (!cpu_has_mips_2_3_4_5_r)
|
|
return SIGILL;
|
|
|
|
handler.u = ieee754dp_sqrt;
|
|
goto dcopuop;
|
|
/*
|
|
* Note that on some MIPS IV implementations such as the
|
|
* R5000 and R8000 the FSQRT and FRECIP instructions do not
|
|
* achieve full IEEE-754 accuracy - however this emulator does.
|
|
*/
|
|
case frsqrt_op:
|
|
if (!cpu_has_mips_4_5_64_r2_r6)
|
|
return SIGILL;
|
|
|
|
handler.u = fpemu_dp_rsqrt;
|
|
goto dcopuop;
|
|
case frecip_op:
|
|
if (!cpu_has_mips_4_5_64_r2_r6)
|
|
return SIGILL;
|
|
|
|
handler.u = fpemu_dp_recip;
|
|
goto dcopuop;
|
|
case fmovc_op:
|
|
if (!cpu_has_mips_4_5_r)
|
|
return SIGILL;
|
|
|
|
cond = fpucondbit[MIPSInst_FT(ir) >> 2];
|
|
if (((ctx->fcr31 & cond) != 0) !=
|
|
((MIPSInst_FT(ir) & 1) != 0))
|
|
return 0;
|
|
DPFROMREG(rv.d, MIPSInst_FS(ir));
|
|
break;
|
|
case fmovz_op:
|
|
if (!cpu_has_mips_4_5_r)
|
|
return SIGILL;
|
|
|
|
if (xcp->regs[MIPSInst_FT(ir)] != 0)
|
|
return 0;
|
|
DPFROMREG(rv.d, MIPSInst_FS(ir));
|
|
break;
|
|
case fmovn_op:
|
|
if (!cpu_has_mips_4_5_r)
|
|
return SIGILL;
|
|
|
|
if (xcp->regs[MIPSInst_FT(ir)] == 0)
|
|
return 0;
|
|
DPFROMREG(rv.d, MIPSInst_FS(ir));
|
|
break;
|
|
case fabs_op:
|
|
handler.u = ieee754dp_abs;
|
|
goto dcopuop;
|
|
|
|
case fneg_op:
|
|
handler.u = ieee754dp_neg;
|
|
goto dcopuop;
|
|
|
|
case fmov_op:
|
|
/* an easy one */
|
|
DPFROMREG(rv.d, MIPSInst_FS(ir));
|
|
goto copcsr;
|
|
|
|
/* binary op on handler */
|
|
dcopbop:
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
DPFROMREG(ft, MIPSInst_FT(ir));
|
|
|
|
rv.d = (*handler.b) (fs, ft);
|
|
goto copcsr;
|
|
dcopuop:
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.d = (*handler.u) (fs);
|
|
goto copcsr;
|
|
|
|
/*
|
|
* unary conv ops
|
|
*/
|
|
case fcvts_op:
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.s = ieee754sp_fdp(fs);
|
|
rfmt = s_fmt;
|
|
goto copcsr;
|
|
|
|
case fcvtd_op:
|
|
return SIGILL; /* not defined */
|
|
|
|
case fcvtw_op:
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.w = ieee754dp_tint(fs); /* wrong */
|
|
rfmt = w_fmt;
|
|
goto copcsr;
|
|
|
|
case fround_op:
|
|
case ftrunc_op:
|
|
case fceil_op:
|
|
case ffloor_op:
|
|
if (!cpu_has_mips_2_3_4_5_r)
|
|
return SIGILL;
|
|
|
|
oldrm = ieee754_csr.rm;
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
ieee754_csr.rm = MIPSInst_FUNC(ir);
|
|
rv.w = ieee754dp_tint(fs);
|
|
ieee754_csr.rm = oldrm;
|
|
rfmt = w_fmt;
|
|
goto copcsr;
|
|
|
|
case fcvtl_op:
|
|
if (!cpu_has_mips_3_4_5_64_r2_r6)
|
|
return SIGILL;
|
|
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.l = ieee754dp_tlong(fs);
|
|
rfmt = l_fmt;
|
|
goto copcsr;
|
|
|
|
case froundl_op:
|
|
case ftruncl_op:
|
|
case fceill_op:
|
|
case ffloorl_op:
|
|
if (!cpu_has_mips_3_4_5_64_r2_r6)
|
|
return SIGILL;
|
|
|
|
oldrm = ieee754_csr.rm;
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
ieee754_csr.rm = MIPSInst_FUNC(ir);
|
|
rv.l = ieee754dp_tlong(fs);
|
|
ieee754_csr.rm = oldrm;
|
|
rfmt = l_fmt;
|
|
goto copcsr;
|
|
|
|
default:
|
|
if (MIPSInst_FUNC(ir) >= fcmp_op) {
|
|
unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
|
|
union ieee754dp fs, ft;
|
|
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
DPFROMREG(ft, MIPSInst_FT(ir));
|
|
rv.w = ieee754dp_cmp(fs, ft,
|
|
cmptab[cmpop & 0x7], cmpop & 0x8);
|
|
rfmt = -1;
|
|
if ((cmpop & 0x8)
|
|
&&
|
|
ieee754_cxtest
|
|
(IEEE754_INVALID_OPERATION))
|
|
rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
|
|
else
|
|
goto copcsr;
|
|
|
|
}
|
|
else {
|
|
return SIGILL;
|
|
}
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case w_fmt:
|
|
switch (MIPSInst_FUNC(ir)) {
|
|
case fcvts_op:
|
|
/* convert word to single precision real */
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.s = ieee754sp_fint(fs.bits);
|
|
rfmt = s_fmt;
|
|
goto copcsr;
|
|
case fcvtd_op:
|
|
/* convert word to double precision real */
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.d = ieee754dp_fint(fs.bits);
|
|
rfmt = d_fmt;
|
|
goto copcsr;
|
|
default:
|
|
return SIGILL;
|
|
}
|
|
break;
|
|
}
|
|
|
|
case l_fmt:
|
|
|
|
if (!cpu_has_mips_3_4_5_64_r2_r6)
|
|
return SIGILL;
|
|
|
|
DIFROMREG(bits, MIPSInst_FS(ir));
|
|
|
|
switch (MIPSInst_FUNC(ir)) {
|
|
case fcvts_op:
|
|
/* convert long to single precision real */
|
|
rv.s = ieee754sp_flong(bits);
|
|
rfmt = s_fmt;
|
|
goto copcsr;
|
|
case fcvtd_op:
|
|
/* convert long to double precision real */
|
|
rv.d = ieee754dp_flong(bits);
|
|
rfmt = d_fmt;
|
|
goto copcsr;
|
|
default:
|
|
return SIGILL;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
return SIGILL;
|
|
}
|
|
|
|
/*
|
|
* Update the fpu CSR register for this operation.
|
|
* If an exception is required, generate a tidy SIGFPE exception,
|
|
* without updating the result register.
|
|
* Note: cause exception bits do not accumulate, they are rewritten
|
|
* for each op; only the flag/sticky bits accumulate.
|
|
*/
|
|
ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
|
|
if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
|
|
/*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
|
|
return SIGFPE;
|
|
}
|
|
|
|
/*
|
|
* Now we can safely write the result back to the register file.
|
|
*/
|
|
switch (rfmt) {
|
|
case -1:
|
|
|
|
if (cpu_has_mips_4_5_r)
|
|
cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
|
|
else
|
|
cbit = FPU_CSR_COND;
|
|
if (rv.w)
|
|
ctx->fcr31 |= cbit;
|
|
else
|
|
ctx->fcr31 &= ~cbit;
|
|
break;
|
|
|
|
case d_fmt:
|
|
DPTOREG(rv.d, MIPSInst_FD(ir));
|
|
break;
|
|
case s_fmt:
|
|
SPTOREG(rv.s, MIPSInst_FD(ir));
|
|
break;
|
|
case w_fmt:
|
|
SITOREG(rv.w, MIPSInst_FD(ir));
|
|
break;
|
|
case l_fmt:
|
|
if (!cpu_has_mips_3_4_5_64_r2_r6)
|
|
return SIGILL;
|
|
|
|
DITOREG(rv.l, MIPSInst_FD(ir));
|
|
break;
|
|
default:
|
|
return SIGILL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
|
int has_fpu, void *__user *fault_addr)
|
|
{
|
|
unsigned long oldepc, prevepc;
|
|
struct mm_decoded_insn dec_insn;
|
|
u16 instr[4];
|
|
u16 *instr_ptr;
|
|
int sig = 0;
|
|
|
|
oldepc = xcp->cp0_epc;
|
|
do {
|
|
prevepc = xcp->cp0_epc;
|
|
|
|
if (get_isa16_mode(prevepc) && cpu_has_mmips) {
|
|
/*
|
|
* Get next 2 microMIPS instructions and convert them
|
|
* into 32-bit instructions.
|
|
*/
|
|
if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
|
|
(get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
|
|
(get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
|
|
(get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
return SIGBUS;
|
|
}
|
|
instr_ptr = instr;
|
|
|
|
/* Get first instruction. */
|
|
if (mm_insn_16bit(*instr_ptr)) {
|
|
/* Duplicate the half-word. */
|
|
dec_insn.insn = (*instr_ptr << 16) |
|
|
(*instr_ptr);
|
|
/* 16-bit instruction. */
|
|
dec_insn.pc_inc = 2;
|
|
instr_ptr += 1;
|
|
} else {
|
|
dec_insn.insn = (*instr_ptr << 16) |
|
|
*(instr_ptr+1);
|
|
/* 32-bit instruction. */
|
|
dec_insn.pc_inc = 4;
|
|
instr_ptr += 2;
|
|
}
|
|
/* Get second instruction. */
|
|
if (mm_insn_16bit(*instr_ptr)) {
|
|
/* Duplicate the half-word. */
|
|
dec_insn.next_insn = (*instr_ptr << 16) |
|
|
(*instr_ptr);
|
|
/* 16-bit instruction. */
|
|
dec_insn.next_pc_inc = 2;
|
|
} else {
|
|
dec_insn.next_insn = (*instr_ptr << 16) |
|
|
*(instr_ptr+1);
|
|
/* 32-bit instruction. */
|
|
dec_insn.next_pc_inc = 4;
|
|
}
|
|
dec_insn.micro_mips_mode = 1;
|
|
} else {
|
|
if ((get_user(dec_insn.insn,
|
|
(mips_instruction __user *) xcp->cp0_epc)) ||
|
|
(get_user(dec_insn.next_insn,
|
|
(mips_instruction __user *)(xcp->cp0_epc+4)))) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
return SIGBUS;
|
|
}
|
|
dec_insn.pc_inc = 4;
|
|
dec_insn.next_pc_inc = 4;
|
|
dec_insn.micro_mips_mode = 0;
|
|
}
|
|
|
|
if ((dec_insn.insn == 0) ||
|
|
((dec_insn.pc_inc == 2) &&
|
|
((dec_insn.insn & 0xffff) == MM_NOP16)))
|
|
xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
|
|
else {
|
|
/*
|
|
* The 'ieee754_csr' is an alias of ctx->fcr31.
|
|
* No need to copy ctx->fcr31 to ieee754_csr.
|
|
*/
|
|
sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
|
|
}
|
|
|
|
if (has_fpu)
|
|
break;
|
|
if (sig)
|
|
break;
|
|
|
|
cond_resched();
|
|
} while (xcp->cp0_epc > prevepc);
|
|
|
|
/* SIGILL indicates a non-fpu instruction */
|
|
if (sig == SIGILL && xcp->cp0_epc != oldepc)
|
|
/* but if EPC has advanced, then ignore it */
|
|
sig = 0;
|
|
|
|
return sig;
|
|
}
|