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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-03 15:16:45 +07:00
585fa72493
On the 34K the redundant cache operations were causing excessive stalls
resulting in realtime code running on the second VPE missing its deadline.
For all other platforms this patch is just a significant performance
improvment as illustrated by below benchmark numbers.
Processor, Processes - times in microseconds - smaller is better
------------------------------------------------------------------------------
Host OS Mhz null null open slct sig sig fork exec sh
call I/O stat clos TCP inst hndl proc proc proc
--------- ------------- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
25Kf 2.6.18-rc4 533 0.49 1.16 7.57 33.4 30.5 1.34 12.4 5497 17.K 54.K
25Kf 2.6.18-rc4-p 533 0.49 1.16 6.68 23.0 30.7 1.36 8.55 5030 16.K 48.K
4Kc 2.6.18-rc4 80 4.21 15.0 131. 289. 261. 16.5 258. 18.K 70.K 227K
4Kc 2.6.18-rc4-p 80 4.34 13.1 128. 285. 262. 18.2 258. 12.K 52.K 176K
34Kc 2.6.18-rc4 40 5.01 14.0 61.6 90.0 477. 17.9 94.7 29.K 108K 342K
34Kc 2.6.18-rc4-p 40 4.98 13.9 61.2 89.7 475. 17.6 93.7 8758 44.K 158K
BCM1480 2.6.18-rc4 700 0.28 0.60 3.68 5.92 16.0 0.78 5.08 931. 3163 15.K
BCM1480 2.6.18-rc4-p 700 0.28 0.61 3.65 5.85 16.0 0.79 5.20 395. 1464 8385
TX49-16K 2.6.18-rc3 197 0.73 2.41 19.0 37.8 82.9 2.94 17.5 4438 14.K 56.K
TX49-16K 2.6.18-rc3-p 197 0.73 2.40 19.9 36.3 82.9 2.94 23.4 2577 9103 38.K
TX49-32K 2.6.18-rc3 396 0.36 1.19 6.80 11.8 41.0 1.46 8.17 2738 8465 32.K
TX49-32K 2.6.18-rc3-p 396 0.36 1.19 6.82 10.2 41.0 1.46 8.18 1330 4638 18.K
Original patch by me with enhancements by Atsushi Nemoto.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
357 lines
8.0 KiB
C
357 lines
8.0 KiB
C
/*
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* r2300.c: R2000 and R3000 specific mmu/cache code.
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*
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* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
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*
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* with a lot of changes to make this thing work for R3000s
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* Tx39XX R4k style caches added. HK
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* Copyright (C) 1998, 1999, 2000 Harald Koerfgen
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* Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
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* Copyright (C) 2001, 2004 Maciej W. Rozycki
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/mmu_context.h>
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#include <asm/system.h>
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#include <asm/isadep.h>
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#include <asm/io.h>
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#include <asm/bootinfo.h>
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#include <asm/cpu.h>
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static unsigned long icache_size, dcache_size; /* Size in bytes */
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static unsigned long icache_lsize, dcache_lsize; /* Size in bytes */
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#undef DEBUG_CACHE
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unsigned long __init r3k_cache_size(unsigned long ca_flags)
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{
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unsigned long flags, status, dummy, size;
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volatile unsigned long *p;
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p = (volatile unsigned long *) KSEG0;
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flags = read_c0_status();
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/* isolate cache space */
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write_c0_status((ca_flags|flags)&~ST0_IEC);
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*p = 0xa5a55a5a;
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dummy = *p;
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status = read_c0_status();
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if (dummy != 0xa5a55a5a || (status & ST0_CM)) {
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size = 0;
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} else {
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for (size = 128; size <= 0x40000; size <<= 1)
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*(p + size) = 0;
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*p = -1;
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for (size = 128;
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(size <= 0x40000) && (*(p + size) == 0);
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size <<= 1)
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;
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if (size > 0x40000)
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size = 0;
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}
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write_c0_status(flags);
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return size * sizeof(*p);
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}
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unsigned long __init r3k_cache_lsize(unsigned long ca_flags)
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{
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unsigned long flags, status, lsize, i;
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volatile unsigned long *p;
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p = (volatile unsigned long *) KSEG0;
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flags = read_c0_status();
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/* isolate cache space */
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write_c0_status((ca_flags|flags)&~ST0_IEC);
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for (i = 0; i < 128; i++)
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*(p + i) = 0;
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*(volatile unsigned char *)p = 0;
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for (lsize = 1; lsize < 128; lsize <<= 1) {
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*(p + lsize);
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status = read_c0_status();
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if (!(status & ST0_CM))
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break;
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}
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for (i = 0; i < 128; i += lsize)
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*(volatile unsigned char *)(p + i) = 0;
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write_c0_status(flags);
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return lsize * sizeof(*p);
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}
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static void __init r3k_probe_cache(void)
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{
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dcache_size = r3k_cache_size(ST0_ISC);
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if (dcache_size)
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dcache_lsize = r3k_cache_lsize(ST0_ISC);
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icache_size = r3k_cache_size(ST0_ISC|ST0_SWC);
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if (icache_size)
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icache_lsize = r3k_cache_lsize(ST0_ISC|ST0_SWC);
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}
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static void r3k_flush_icache_range(unsigned long start, unsigned long end)
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{
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unsigned long size, i, flags;
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volatile unsigned char *p;
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size = end - start;
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if (size > icache_size || KSEGX(start) != KSEG0) {
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start = KSEG0;
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size = icache_size;
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}
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p = (char *)start;
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flags = read_c0_status();
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/* isolate cache space */
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write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC);
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for (i = 0; i < size; i += 0x080) {
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asm ( "sb\t$0, 0x000(%0)\n\t"
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"sb\t$0, 0x004(%0)\n\t"
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"sb\t$0, 0x008(%0)\n\t"
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"sb\t$0, 0x00c(%0)\n\t"
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"sb\t$0, 0x010(%0)\n\t"
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"sb\t$0, 0x014(%0)\n\t"
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"sb\t$0, 0x018(%0)\n\t"
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"sb\t$0, 0x01c(%0)\n\t"
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"sb\t$0, 0x020(%0)\n\t"
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"sb\t$0, 0x024(%0)\n\t"
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"sb\t$0, 0x028(%0)\n\t"
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"sb\t$0, 0x02c(%0)\n\t"
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"sb\t$0, 0x030(%0)\n\t"
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"sb\t$0, 0x034(%0)\n\t"
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"sb\t$0, 0x038(%0)\n\t"
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"sb\t$0, 0x03c(%0)\n\t"
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"sb\t$0, 0x040(%0)\n\t"
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"sb\t$0, 0x044(%0)\n\t"
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"sb\t$0, 0x048(%0)\n\t"
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"sb\t$0, 0x04c(%0)\n\t"
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"sb\t$0, 0x050(%0)\n\t"
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"sb\t$0, 0x054(%0)\n\t"
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"sb\t$0, 0x058(%0)\n\t"
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"sb\t$0, 0x05c(%0)\n\t"
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"sb\t$0, 0x060(%0)\n\t"
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"sb\t$0, 0x064(%0)\n\t"
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"sb\t$0, 0x068(%0)\n\t"
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"sb\t$0, 0x06c(%0)\n\t"
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"sb\t$0, 0x070(%0)\n\t"
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"sb\t$0, 0x074(%0)\n\t"
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"sb\t$0, 0x078(%0)\n\t"
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"sb\t$0, 0x07c(%0)\n\t"
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: : "r" (p) );
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p += 0x080;
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}
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write_c0_status(flags);
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}
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static void r3k_flush_dcache_range(unsigned long start, unsigned long end)
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{
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unsigned long size, i, flags;
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volatile unsigned char *p;
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size = end - start;
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if (size > dcache_size || KSEGX(start) != KSEG0) {
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start = KSEG0;
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size = dcache_size;
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}
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p = (char *)start;
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flags = read_c0_status();
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/* isolate cache space */
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write_c0_status((ST0_ISC|flags)&~ST0_IEC);
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for (i = 0; i < size; i += 0x080) {
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asm ( "sb\t$0, 0x000(%0)\n\t"
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"sb\t$0, 0x004(%0)\n\t"
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"sb\t$0, 0x008(%0)\n\t"
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"sb\t$0, 0x00c(%0)\n\t"
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"sb\t$0, 0x010(%0)\n\t"
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"sb\t$0, 0x014(%0)\n\t"
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"sb\t$0, 0x018(%0)\n\t"
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"sb\t$0, 0x01c(%0)\n\t"
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"sb\t$0, 0x020(%0)\n\t"
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"sb\t$0, 0x024(%0)\n\t"
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"sb\t$0, 0x028(%0)\n\t"
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"sb\t$0, 0x02c(%0)\n\t"
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"sb\t$0, 0x030(%0)\n\t"
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"sb\t$0, 0x034(%0)\n\t"
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"sb\t$0, 0x038(%0)\n\t"
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"sb\t$0, 0x03c(%0)\n\t"
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"sb\t$0, 0x040(%0)\n\t"
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"sb\t$0, 0x044(%0)\n\t"
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"sb\t$0, 0x048(%0)\n\t"
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"sb\t$0, 0x04c(%0)\n\t"
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"sb\t$0, 0x050(%0)\n\t"
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"sb\t$0, 0x054(%0)\n\t"
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"sb\t$0, 0x058(%0)\n\t"
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"sb\t$0, 0x05c(%0)\n\t"
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"sb\t$0, 0x060(%0)\n\t"
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"sb\t$0, 0x064(%0)\n\t"
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"sb\t$0, 0x068(%0)\n\t"
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"sb\t$0, 0x06c(%0)\n\t"
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"sb\t$0, 0x070(%0)\n\t"
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"sb\t$0, 0x074(%0)\n\t"
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"sb\t$0, 0x078(%0)\n\t"
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"sb\t$0, 0x07c(%0)\n\t"
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: : "r" (p) );
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p += 0x080;
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}
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write_c0_status(flags);
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}
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static inline unsigned long get_phys_page (unsigned long addr,
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struct mm_struct *mm)
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{
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pgd_t *pgd;
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pud_t *pud;
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pmd_t *pmd;
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pte_t *pte;
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unsigned long physpage;
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pgd = pgd_offset(mm, addr);
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pud = pud_offset(pgd, addr);
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pmd = pmd_offset(pud, addr);
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pte = pte_offset(pmd, addr);
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if ((physpage = pte_val(*pte)) & _PAGE_VALID)
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return KSEG0ADDR(physpage & PAGE_MASK);
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return 0;
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}
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static inline void r3k_flush_cache_all(void)
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{
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}
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static inline void r3k___flush_cache_all(void)
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{
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r3k_flush_dcache_range(KSEG0, KSEG0 + dcache_size);
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r3k_flush_icache_range(KSEG0, KSEG0 + icache_size);
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}
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static void r3k_flush_cache_mm(struct mm_struct *mm)
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{
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}
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static void r3k_flush_cache_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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}
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static void r3k_flush_cache_page(struct vm_area_struct *vma, unsigned long page, unsigned long pfn)
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{
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}
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static void local_r3k_flush_data_cache_page(unsigned long addr)
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{
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}
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static void r3k_flush_data_cache_page(unsigned long addr)
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{
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}
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static void r3k_flush_icache_page(struct vm_area_struct *vma, struct page *page)
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{
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struct mm_struct *mm = vma->vm_mm;
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unsigned long physpage;
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if (cpu_context(smp_processor_id(), mm) == 0)
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return;
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if (!(vma->vm_flags & VM_EXEC))
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return;
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#ifdef DEBUG_CACHE
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printk("cpage[%d,%08lx]", cpu_context(smp_processor_id(), mm), page);
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#endif
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physpage = (unsigned long) page_address(page);
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if (physpage)
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r3k_flush_icache_range(physpage, physpage + PAGE_SIZE);
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}
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static void r3k_flush_cache_sigtramp(unsigned long addr)
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{
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unsigned long flags;
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#ifdef DEBUG_CACHE
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printk("csigtramp[%08lx]", addr);
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#endif
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flags = read_c0_status();
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write_c0_status(flags&~ST0_IEC);
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/* Fill the TLB to avoid an exception with caches isolated. */
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asm ( "lw\t$0, 0x000(%0)\n\t"
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"lw\t$0, 0x004(%0)\n\t"
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: : "r" (addr) );
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write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC);
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asm ( "sb\t$0, 0x000(%0)\n\t"
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"sb\t$0, 0x004(%0)\n\t"
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: : "r" (addr) );
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write_c0_status(flags);
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}
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static void r3k_dma_cache_wback_inv(unsigned long start, unsigned long size)
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{
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/* Catch bad driver code */
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BUG_ON(size == 0);
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iob();
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r3k_flush_dcache_range(start, start + size);
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}
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void __init r3k_cache_init(void)
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{
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extern void build_clear_page(void);
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extern void build_copy_page(void);
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r3k_probe_cache();
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flush_cache_all = r3k_flush_cache_all;
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__flush_cache_all = r3k___flush_cache_all;
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flush_cache_mm = r3k_flush_cache_mm;
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flush_cache_range = r3k_flush_cache_range;
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flush_cache_page = r3k_flush_cache_page;
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__flush_icache_page = r3k_flush_icache_page;
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flush_icache_range = r3k_flush_icache_range;
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flush_cache_sigtramp = r3k_flush_cache_sigtramp;
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local_flush_data_cache_page = local_r3k_flush_data_cache_page;
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flush_data_cache_page = r3k_flush_data_cache_page;
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_dma_cache_wback_inv = r3k_dma_cache_wback_inv;
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_dma_cache_wback = r3k_dma_cache_wback_inv;
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_dma_cache_inv = r3k_dma_cache_wback_inv;
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printk("Primary instruction cache %ldkB, linesize %ld bytes.\n",
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icache_size >> 10, icache_lsize);
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printk("Primary data cache %ldkB, linesize %ld bytes.\n",
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dcache_size >> 10, dcache_lsize);
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build_clear_page();
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build_copy_page();
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}
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