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5b5c4e40a3
This patch adds the topology module to the driver. The topology is exposed to
userspace through the sysfs.
The calls to add and remove a device to/from topology are done by the radeon
driver.
v3:
The CPU information, that is provided in the topology section of the amdkfd
driver, is extracted from the CRAT table. Unlike the CPU information located
in /sys/devices/system/cpu/cpu*, which is extracted from the SRAT table.
While the CPU information provided by the CRAT and the SRAT tables might be
identical, the node topology might be different. The SRAT table contains the
topology of CPU nodes only. The CRAT table contains the topology of CPU and GPU
nodes together (and can be interleaved). For example CPU node 1 in SRAT can be
CPU node 3 in CRAT. Furthermore it's worth to mention that the CRAT table
contains only HSA compatible nodes (nodes which are compliant with the HSA
spec).
To recap, amdkfd exposes a different kind of topology than the one exposed by
/sys/devices/system/cpu/cpu even though it may contain similar information.
v4:
The topology module doesn't support uevent handling and doesn't notify the
userspace about runtime modifications. It is up to the userspace to acquire
snapshots of the topology information created by the amdkfd and exposed
in sysfs.
The following is an example of how the topology looks on a Kaveri A10-7850K
system with amdkfd installed:
/sys/devices/virtual/kfd/kfd/
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--- topology/
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|--- generation_id
|--- system_properties
|--- nodes/
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|--- 0/
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|--- gpu_id
|--- name
|--- properties
|--- caches/
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|--- 0/
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|--- properties
|--- 1/
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|--- properties
|--- 2/
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|--- properties
|--- io_links/
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|--- mem_banks/
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|--- 0/
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|--- properties
|--- 1/
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|--- properties
|--- 2/
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|--- properties
|--- 3/
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|--- properties
v5:
Move amdkfd from drm/radeon/ to drm/amd/
Add a check if dev->gpu pointer is null before accessing it in the
node_show function in kfd_topology.c
This situation may occur when amdkfd is loaded and there is a GPU with a CRAT
table, but that GPU isn't supported by amdkfd
Signed-off-by: Evgeny Pinchuk <evgeny.pinchuk@amd.com>
Signed-off-by: Oded Gabbay <oded.gabbay@amd.com>
169 lines
4.8 KiB
C
169 lines
4.8 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __KFD_TOPOLOGY_H__
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#define __KFD_TOPOLOGY_H__
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#include <linux/types.h>
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#include <linux/list.h>
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#include "kfd_priv.h"
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#define KFD_TOPOLOGY_PUBLIC_NAME_SIZE 128
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#define HSA_CAP_HOT_PLUGGABLE 0x00000001
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#define HSA_CAP_ATS_PRESENT 0x00000002
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#define HSA_CAP_SHARED_WITH_GRAPHICS 0x00000004
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#define HSA_CAP_QUEUE_SIZE_POW2 0x00000008
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#define HSA_CAP_QUEUE_SIZE_32BIT 0x00000010
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#define HSA_CAP_QUEUE_IDLE_EVENT 0x00000020
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#define HSA_CAP_VA_LIMIT 0x00000040
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#define HSA_CAP_WATCH_POINTS_SUPPORTED 0x00000080
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#define HSA_CAP_WATCH_POINTS_TOTALBITS_MASK 0x00000f00
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#define HSA_CAP_WATCH_POINTS_TOTALBITS_SHIFT 8
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#define HSA_CAP_RESERVED 0xfffff000
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struct kfd_node_properties {
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uint32_t cpu_cores_count;
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uint32_t simd_count;
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uint32_t mem_banks_count;
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uint32_t caches_count;
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uint32_t io_links_count;
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uint32_t cpu_core_id_base;
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uint32_t simd_id_base;
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uint32_t capability;
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uint32_t max_waves_per_simd;
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uint32_t lds_size_in_kb;
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uint32_t gds_size_in_kb;
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uint32_t wave_front_size;
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uint32_t array_count;
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uint32_t simd_arrays_per_engine;
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uint32_t cu_per_simd_array;
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uint32_t simd_per_cu;
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uint32_t max_slots_scratch_cu;
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uint32_t engine_id;
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uint32_t vendor_id;
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uint32_t device_id;
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uint32_t location_id;
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uint32_t max_engine_clk_fcompute;
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uint32_t max_engine_clk_ccompute;
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uint16_t marketing_name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE];
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};
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#define HSA_MEM_HEAP_TYPE_SYSTEM 0
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#define HSA_MEM_HEAP_TYPE_FB_PUBLIC 1
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#define HSA_MEM_HEAP_TYPE_FB_PRIVATE 2
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#define HSA_MEM_HEAP_TYPE_GPU_GDS 3
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#define HSA_MEM_HEAP_TYPE_GPU_LDS 4
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#define HSA_MEM_HEAP_TYPE_GPU_SCRATCH 5
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#define HSA_MEM_FLAGS_HOT_PLUGGABLE 0x00000001
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#define HSA_MEM_FLAGS_NON_VOLATILE 0x00000002
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#define HSA_MEM_FLAGS_RESERVED 0xfffffffc
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struct kfd_mem_properties {
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struct list_head list;
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uint32_t heap_type;
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uint64_t size_in_bytes;
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uint32_t flags;
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uint32_t width;
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uint32_t mem_clk_max;
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struct kobject *kobj;
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struct attribute attr;
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};
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#define KFD_TOPOLOGY_CPU_SIBLINGS 256
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#define HSA_CACHE_TYPE_DATA 0x00000001
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#define HSA_CACHE_TYPE_INSTRUCTION 0x00000002
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#define HSA_CACHE_TYPE_CPU 0x00000004
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#define HSA_CACHE_TYPE_HSACU 0x00000008
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#define HSA_CACHE_TYPE_RESERVED 0xfffffff0
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struct kfd_cache_properties {
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struct list_head list;
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uint32_t processor_id_low;
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uint32_t cache_level;
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uint32_t cache_size;
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uint32_t cacheline_size;
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uint32_t cachelines_per_tag;
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uint32_t cache_assoc;
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uint32_t cache_latency;
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uint32_t cache_type;
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uint8_t sibling_map[KFD_TOPOLOGY_CPU_SIBLINGS];
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struct kobject *kobj;
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struct attribute attr;
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};
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struct kfd_iolink_properties {
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struct list_head list;
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uint32_t iolink_type;
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uint32_t ver_maj;
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uint32_t ver_min;
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uint32_t node_from;
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uint32_t node_to;
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uint32_t weight;
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uint32_t min_latency;
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uint32_t max_latency;
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uint32_t min_bandwidth;
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uint32_t max_bandwidth;
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uint32_t rec_transfer_size;
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uint32_t flags;
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struct kobject *kobj;
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struct attribute attr;
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};
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struct kfd_topology_device {
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struct list_head list;
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uint32_t gpu_id;
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struct kfd_node_properties node_props;
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uint32_t mem_bank_count;
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struct list_head mem_props;
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uint32_t cache_count;
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struct list_head cache_props;
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uint32_t io_link_count;
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struct list_head io_link_props;
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struct kfd_dev *gpu;
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struct kobject *kobj_node;
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struct kobject *kobj_mem;
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struct kobject *kobj_cache;
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struct kobject *kobj_iolink;
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struct attribute attr_gpuid;
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struct attribute attr_name;
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struct attribute attr_props;
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};
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struct kfd_system_properties {
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uint32_t num_devices; /* Number of H-NUMA nodes */
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uint32_t generation_count;
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uint64_t platform_oem;
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uint64_t platform_id;
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uint64_t platform_rev;
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struct kobject *kobj_topology;
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struct kobject *kobj_nodes;
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struct attribute attr_genid;
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struct attribute attr_props;
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};
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#endif /* __KFD_TOPOLOGY_H__ */
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