mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 06:26:48 +07:00
fc89a57600
K2E SoC has a second PCI port based on Synopsis Designware PCIe h/w. Add DT bindings to support PCI controller for port 1 for this SoC. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
139 lines
3.2 KiB
Plaintext
139 lines
3.2 KiB
Plaintext
/*
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* Copyright 2013-2014 Texas Instruments, Inc.
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*
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* Keystone 2 Edison soc device tree
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&gic>;
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cpu@0 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <0>;
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};
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cpu@1 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <1>;
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};
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cpu@2 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <2>;
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};
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cpu@3 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <3>;
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};
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};
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soc {
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/include/ "k2e-clocks.dtsi"
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usb: usb@2680000 {
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interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
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dwc3@2690000 {
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interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>;
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};
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};
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usb1_phy: usb_phy@2620750 {
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compatible = "ti,keystone-usbphy";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x2620750 24>;
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status = "disabled";
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};
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usb1: usb@25000000 {
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compatible = "ti,keystone-dwc3";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x25000000 0x10000>;
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clocks = <&clkusb1>;
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clock-names = "usb";
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interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>;
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ranges;
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dma-coherent;
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dma-ranges;
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status = "disabled";
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dwc3@25010000 {
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compatible = "synopsys,dwc3";
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reg = <0x25010000 0x70000>;
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interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>;
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usb-phy = <&usb1_phy>, <&usb1_phy>;
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};
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};
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dspgpio0: keystone_dsp_gpio@02620240 {
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compatible = "ti,keystone-dsp-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio,syscon-dev = <&devctrl 0x240>;
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};
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pcie@21020000 {
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compatible = "ti,keystone-pcie","snps,dw-pcie";
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clocks = <&clkpcie1>;
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clock-names = "pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
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ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000
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0x82000000 0 0x60000000 0x60000000 0 0x10000000>;
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device_type = "pci";
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num-lanes = <2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */
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<0 0 0 2 &pcie_intc1 1>, /* INT B */
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<0 0 0 3 &pcie_intc1 2>, /* INT C */
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<0 0 0 4 &pcie_intc1 3>; /* INT D */
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pcie_msi_intc1: msi-interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 379 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 380 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 381 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 382 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 383 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 384 IRQ_TYPE_EDGE_RISING>;
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};
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pcie_intc1: legacy-interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 376 IRQ_TYPE_EDGE_RISING>;
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};
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};
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};
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};
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&mdio {
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reg = <0x24200f00 0x100>;
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};
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