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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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3b74d18e54
Jens has added a partial_page thing in splice whcih conflicts with the ia64 one. Rename ia64 out of the way. (ia64 chose poorly). Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Tony Luck <tony.luck@intel.com>
706 lines
19 KiB
C
706 lines
19 KiB
C
#ifndef _ASM_IA64_PROCESSOR_H
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#define _ASM_IA64_PROCESSOR_H
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/*
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* Copyright (C) 1998-2004 Hewlett-Packard Co
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* David Mosberger-Tang <davidm@hpl.hp.com>
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* Stephane Eranian <eranian@hpl.hp.com>
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* Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
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* Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
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*
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* 11/24/98 S.Eranian added ia64_set_iva()
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* 12/03/99 D. Mosberger implement thread_saved_pc() via kernel unwind API
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* 06/16/00 A. Mallick added csd/ssd/tssd for ia32 support
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*/
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#include <asm/intrinsics.h>
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#include <asm/kregs.h>
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#include <asm/ptrace.h>
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#include <asm/ustack.h>
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#define IA64_NUM_PHYS_STACK_REG 96
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#define IA64_NUM_DBG_REGS 8
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#define DEFAULT_MAP_BASE __IA64_UL_CONST(0x2000000000000000)
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#define DEFAULT_TASK_SIZE __IA64_UL_CONST(0xa000000000000000)
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/*
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* TASK_SIZE really is a mis-named. It really is the maximum user
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* space address (plus one). On IA-64, there are five regions of 2TB
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* each (assuming 8KB page size), for a total of 8TB of user virtual
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* address space.
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*/
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#define TASK_SIZE (current->thread.task_size)
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/*
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* This decides where the kernel will search for a free chunk of vm
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* space during mmap's.
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*/
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#define TASK_UNMAPPED_BASE (current->thread.map_base)
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#define IA64_THREAD_FPH_VALID (__IA64_UL(1) << 0) /* floating-point high state valid? */
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#define IA64_THREAD_DBG_VALID (__IA64_UL(1) << 1) /* debug registers valid? */
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#define IA64_THREAD_PM_VALID (__IA64_UL(1) << 2) /* performance registers valid? */
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#define IA64_THREAD_UAC_NOPRINT (__IA64_UL(1) << 3) /* don't log unaligned accesses */
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#define IA64_THREAD_UAC_SIGBUS (__IA64_UL(1) << 4) /* generate SIGBUS on unaligned acc. */
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#define IA64_THREAD_MIGRATION (__IA64_UL(1) << 5) /* require migration
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sync at ctx sw */
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#define IA64_THREAD_FPEMU_NOPRINT (__IA64_UL(1) << 6) /* don't log any fpswa faults */
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#define IA64_THREAD_FPEMU_SIGFPE (__IA64_UL(1) << 7) /* send a SIGFPE for fpswa faults */
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#define IA64_THREAD_UAC_SHIFT 3
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#define IA64_THREAD_UAC_MASK (IA64_THREAD_UAC_NOPRINT | IA64_THREAD_UAC_SIGBUS)
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#define IA64_THREAD_FPEMU_SHIFT 6
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#define IA64_THREAD_FPEMU_MASK (IA64_THREAD_FPEMU_NOPRINT | IA64_THREAD_FPEMU_SIGFPE)
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/*
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* This shift should be large enough to be able to represent 1000000000/itc_freq with good
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* accuracy while being small enough to fit 10*1000000000<<IA64_NSEC_PER_CYC_SHIFT in 64 bits
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* (this will give enough slack to represent 10 seconds worth of time as a scaled number).
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*/
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#define IA64_NSEC_PER_CYC_SHIFT 30
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#ifndef __ASSEMBLY__
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#include <linux/cache.h>
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#include <linux/compiler.h>
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#include <linux/threads.h>
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#include <linux/types.h>
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#include <asm/fpu.h>
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#include <asm/page.h>
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#include <asm/percpu.h>
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#include <asm/rse.h>
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#include <asm/unwind.h>
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#include <asm/atomic.h>
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#ifdef CONFIG_NUMA
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#include <asm/nodedata.h>
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#endif
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/* like above but expressed as bitfields for more efficient access: */
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struct ia64_psr {
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__u64 reserved0 : 1;
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__u64 be : 1;
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__u64 up : 1;
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__u64 ac : 1;
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__u64 mfl : 1;
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__u64 mfh : 1;
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__u64 reserved1 : 7;
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__u64 ic : 1;
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__u64 i : 1;
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__u64 pk : 1;
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__u64 reserved2 : 1;
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__u64 dt : 1;
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__u64 dfl : 1;
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__u64 dfh : 1;
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__u64 sp : 1;
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__u64 pp : 1;
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__u64 di : 1;
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__u64 si : 1;
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__u64 db : 1;
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__u64 lp : 1;
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__u64 tb : 1;
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__u64 rt : 1;
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__u64 reserved3 : 4;
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__u64 cpl : 2;
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__u64 is : 1;
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__u64 mc : 1;
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__u64 it : 1;
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__u64 id : 1;
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__u64 da : 1;
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__u64 dd : 1;
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__u64 ss : 1;
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__u64 ri : 2;
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__u64 ed : 1;
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__u64 bn : 1;
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__u64 reserved4 : 19;
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};
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/*
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* CPU type, hardware bug flags, and per-CPU state. Frequently used
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* state comes earlier:
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*/
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struct cpuinfo_ia64 {
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__u32 softirq_pending;
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__u64 itm_delta; /* # of clock cycles between clock ticks */
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__u64 itm_next; /* interval timer mask value to use for next clock tick */
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__u64 nsec_per_cyc; /* (1000000000<<IA64_NSEC_PER_CYC_SHIFT)/itc_freq */
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__u64 unimpl_va_mask; /* mask of unimplemented virtual address bits (from PAL) */
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__u64 unimpl_pa_mask; /* mask of unimplemented physical address bits (from PAL) */
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__u64 itc_freq; /* frequency of ITC counter */
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__u64 proc_freq; /* frequency of processor */
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__u64 cyc_per_usec; /* itc_freq/1000000 */
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__u64 ptce_base;
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__u32 ptce_count[2];
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__u32 ptce_stride[2];
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struct task_struct *ksoftirqd; /* kernel softirq daemon for this CPU */
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#ifdef CONFIG_SMP
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__u64 loops_per_jiffy;
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int cpu;
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__u32 socket_id; /* physical processor socket id */
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__u16 core_id; /* core id */
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__u16 thread_id; /* thread id */
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__u16 num_log; /* Total number of logical processors on
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* this socket that were successfully booted */
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__u8 cores_per_socket; /* Cores per processor socket */
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__u8 threads_per_core; /* Threads per core */
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#endif
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/* CPUID-derived information: */
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__u64 ppn;
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__u64 features;
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__u8 number;
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__u8 revision;
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__u8 model;
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__u8 family;
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__u8 archrev;
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char vendor[16];
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char *model_name;
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#ifdef CONFIG_NUMA
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struct ia64_node_data *node_data;
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#endif
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};
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DECLARE_PER_CPU(struct cpuinfo_ia64, cpu_info);
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/*
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* The "local" data variable. It refers to the per-CPU data of the currently executing
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* CPU, much like "current" points to the per-task data of the currently executing task.
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* Do not use the address of local_cpu_data, since it will be different from
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* cpu_data(smp_processor_id())!
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*/
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#define local_cpu_data (&__ia64_per_cpu_var(cpu_info))
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#define cpu_data(cpu) (&per_cpu(cpu_info, cpu))
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extern void print_cpu_info (struct cpuinfo_ia64 *);
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typedef struct {
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unsigned long seg;
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} mm_segment_t;
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#define SET_UNALIGN_CTL(task,value) \
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({ \
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(task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_UAC_MASK) \
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| (((value) << IA64_THREAD_UAC_SHIFT) & IA64_THREAD_UAC_MASK)); \
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0; \
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})
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#define GET_UNALIGN_CTL(task,addr) \
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({ \
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put_user(((task)->thread.flags & IA64_THREAD_UAC_MASK) >> IA64_THREAD_UAC_SHIFT, \
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(int __user *) (addr)); \
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})
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#define SET_FPEMU_CTL(task,value) \
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({ \
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(task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_FPEMU_MASK) \
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| (((value) << IA64_THREAD_FPEMU_SHIFT) & IA64_THREAD_FPEMU_MASK)); \
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0; \
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})
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#define GET_FPEMU_CTL(task,addr) \
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({ \
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put_user(((task)->thread.flags & IA64_THREAD_FPEMU_MASK) >> IA64_THREAD_FPEMU_SHIFT, \
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(int __user *) (addr)); \
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})
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#ifdef CONFIG_IA32_SUPPORT
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struct desc_struct {
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unsigned int a, b;
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};
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#define desc_empty(desc) (!((desc)->a | (desc)->b))
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#define desc_equal(desc1, desc2) (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
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#define GDT_ENTRY_TLS_ENTRIES 3
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#define GDT_ENTRY_TLS_MIN 6
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#define GDT_ENTRY_TLS_MAX (GDT_ENTRY_TLS_MIN + GDT_ENTRY_TLS_ENTRIES - 1)
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#define TLS_SIZE (GDT_ENTRY_TLS_ENTRIES * 8)
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struct ia64_partial_page_list;
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#endif
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struct thread_struct {
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__u32 flags; /* various thread flags (see IA64_THREAD_*) */
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/* writing on_ustack is performance-critical, so it's worth spending 8 bits on it... */
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__u8 on_ustack; /* executing on user-stacks? */
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__u8 pad[3];
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__u64 ksp; /* kernel stack pointer */
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__u64 map_base; /* base address for get_unmapped_area() */
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__u64 task_size; /* limit for task size */
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__u64 rbs_bot; /* the base address for the RBS */
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int last_fph_cpu; /* CPU that may hold the contents of f32-f127 */
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#ifdef CONFIG_IA32_SUPPORT
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__u64 eflag; /* IA32 EFLAGS reg */
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__u64 fsr; /* IA32 floating pt status reg */
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__u64 fcr; /* IA32 floating pt control reg */
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__u64 fir; /* IA32 fp except. instr. reg */
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__u64 fdr; /* IA32 fp except. data reg */
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__u64 old_k1; /* old value of ar.k1 */
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__u64 old_iob; /* old IOBase value */
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struct ia64_partial_page_list *ppl; /* partial page list for 4K page size issue */
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/* cached TLS descriptors. */
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struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
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# define INIT_THREAD_IA32 .eflag = 0, \
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.fsr = 0, \
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.fcr = 0x17800000037fULL, \
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.fir = 0, \
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.fdr = 0, \
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.old_k1 = 0, \
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.old_iob = 0, \
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.ppl = NULL,
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#else
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# define INIT_THREAD_IA32
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#endif /* CONFIG_IA32_SUPPORT */
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#ifdef CONFIG_PERFMON
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void *pfm_context; /* pointer to detailed PMU context */
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unsigned long pfm_needs_checking; /* when >0, pending perfmon work on kernel exit */
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# define INIT_THREAD_PM .pfm_context = NULL, \
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.pfm_needs_checking = 0UL,
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#else
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# define INIT_THREAD_PM
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#endif
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__u64 dbr[IA64_NUM_DBG_REGS];
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__u64 ibr[IA64_NUM_DBG_REGS];
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struct ia64_fpreg fph[96]; /* saved/loaded on demand */
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};
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#define INIT_THREAD { \
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.flags = 0, \
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.on_ustack = 0, \
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.ksp = 0, \
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.map_base = DEFAULT_MAP_BASE, \
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.rbs_bot = STACK_TOP - DEFAULT_USER_STACK_SIZE, \
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.task_size = DEFAULT_TASK_SIZE, \
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.last_fph_cpu = -1, \
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INIT_THREAD_IA32 \
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INIT_THREAD_PM \
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.dbr = {0, }, \
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.ibr = {0, }, \
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.fph = {{{{0}}}, } \
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}
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#define start_thread(regs,new_ip,new_sp) do { \
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set_fs(USER_DS); \
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regs->cr_ipsr = ((regs->cr_ipsr | (IA64_PSR_BITS_TO_SET | IA64_PSR_CPL)) \
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& ~(IA64_PSR_BITS_TO_CLEAR | IA64_PSR_RI | IA64_PSR_IS)); \
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regs->cr_iip = new_ip; \
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regs->ar_rsc = 0xf; /* eager mode, privilege level 3 */ \
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regs->ar_rnat = 0; \
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regs->ar_bspstore = current->thread.rbs_bot; \
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regs->ar_fpsr = FPSR_DEFAULT; \
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regs->loadrs = 0; \
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regs->r8 = get_dumpable(current->mm); /* set "don't zap registers" flag */ \
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regs->r12 = new_sp - 16; /* allocate 16 byte scratch area */ \
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if (unlikely(!get_dumpable(current->mm))) { \
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/* \
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* Zap scratch regs to avoid leaking bits between processes with different \
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* uid/privileges. \
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*/ \
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regs->ar_pfs = 0; regs->b0 = 0; regs->pr = 0; \
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regs->r1 = 0; regs->r9 = 0; regs->r11 = 0; regs->r13 = 0; regs->r15 = 0; \
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} \
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} while (0)
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/* Forward declarations, a strange C thing... */
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struct mm_struct;
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struct task_struct;
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/*
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* Free all resources held by a thread. This is called after the
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* parent of DEAD_TASK has collected the exit status of the task via
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* wait().
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*/
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#define release_thread(dead_task)
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/* Prepare to copy thread state - unlazy all lazy status */
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#define prepare_to_copy(tsk) do { } while (0)
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/*
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* This is the mechanism for creating a new kernel thread.
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*
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* NOTE 1: Only a kernel-only process (ie the swapper or direct
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* descendants who haven't done an "execve()") should use this: it
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* will work within a system call from a "real" process, but the
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* process memory space will not be free'd until both the parent and
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* the child have exited.
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*
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* NOTE 2: This MUST NOT be an inlined function. Otherwise, we get
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* into trouble in init/main.c when the child thread returns to
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* do_basic_setup() and the timing is such that free_initmem() has
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* been called already.
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*/
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extern pid_t kernel_thread (int (*fn)(void *), void *arg, unsigned long flags);
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/* Get wait channel for task P. */
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extern unsigned long get_wchan (struct task_struct *p);
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/* Return instruction pointer of blocked task TSK. */
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#define KSTK_EIP(tsk) \
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({ \
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struct pt_regs *_regs = task_pt_regs(tsk); \
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_regs->cr_iip + ia64_psr(_regs)->ri; \
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})
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/* Return stack pointer of blocked task TSK. */
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#define KSTK_ESP(tsk) ((tsk)->thread.ksp)
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extern void ia64_getreg_unknown_kr (void);
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extern void ia64_setreg_unknown_kr (void);
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#define ia64_get_kr(regnum) \
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({ \
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unsigned long r = 0; \
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\
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switch (regnum) { \
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case 0: r = ia64_getreg(_IA64_REG_AR_KR0); break; \
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case 1: r = ia64_getreg(_IA64_REG_AR_KR1); break; \
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case 2: r = ia64_getreg(_IA64_REG_AR_KR2); break; \
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case 3: r = ia64_getreg(_IA64_REG_AR_KR3); break; \
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case 4: r = ia64_getreg(_IA64_REG_AR_KR4); break; \
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case 5: r = ia64_getreg(_IA64_REG_AR_KR5); break; \
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case 6: r = ia64_getreg(_IA64_REG_AR_KR6); break; \
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case 7: r = ia64_getreg(_IA64_REG_AR_KR7); break; \
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default: ia64_getreg_unknown_kr(); break; \
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} \
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r; \
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})
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#define ia64_set_kr(regnum, r) \
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({ \
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switch (regnum) { \
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case 0: ia64_setreg(_IA64_REG_AR_KR0, r); break; \
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case 1: ia64_setreg(_IA64_REG_AR_KR1, r); break; \
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case 2: ia64_setreg(_IA64_REG_AR_KR2, r); break; \
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case 3: ia64_setreg(_IA64_REG_AR_KR3, r); break; \
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case 4: ia64_setreg(_IA64_REG_AR_KR4, r); break; \
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case 5: ia64_setreg(_IA64_REG_AR_KR5, r); break; \
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case 6: ia64_setreg(_IA64_REG_AR_KR6, r); break; \
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case 7: ia64_setreg(_IA64_REG_AR_KR7, r); break; \
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default: ia64_setreg_unknown_kr(); break; \
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} \
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})
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/*
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* The following three macros can't be inline functions because we don't have struct
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* task_struct at this point.
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*/
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/*
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* Return TRUE if task T owns the fph partition of the CPU we're running on.
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* Must be called from code that has preemption disabled.
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*/
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#define ia64_is_local_fpu_owner(t) \
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({ \
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struct task_struct *__ia64_islfo_task = (t); \
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(__ia64_islfo_task->thread.last_fph_cpu == smp_processor_id() \
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&& __ia64_islfo_task == (struct task_struct *) ia64_get_kr(IA64_KR_FPU_OWNER)); \
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})
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/*
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* Mark task T as owning the fph partition of the CPU we're running on.
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* Must be called from code that has preemption disabled.
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*/
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#define ia64_set_local_fpu_owner(t) do { \
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struct task_struct *__ia64_slfo_task = (t); \
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__ia64_slfo_task->thread.last_fph_cpu = smp_processor_id(); \
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ia64_set_kr(IA64_KR_FPU_OWNER, (unsigned long) __ia64_slfo_task); \
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} while (0)
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/* Mark the fph partition of task T as being invalid on all CPUs. */
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#define ia64_drop_fpu(t) ((t)->thread.last_fph_cpu = -1)
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extern void __ia64_init_fpu (void);
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extern void __ia64_save_fpu (struct ia64_fpreg *fph);
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extern void __ia64_load_fpu (struct ia64_fpreg *fph);
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extern void ia64_save_debug_regs (unsigned long *save_area);
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extern void ia64_load_debug_regs (unsigned long *save_area);
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#ifdef CONFIG_IA32_SUPPORT
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extern void ia32_save_state (struct task_struct *task);
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extern void ia32_load_state (struct task_struct *task);
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#endif
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#define ia64_fph_enable() do { ia64_rsm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
|
|
#define ia64_fph_disable() do { ia64_ssm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
|
|
|
|
/* load fp 0.0 into fph */
|
|
static inline void
|
|
ia64_init_fpu (void) {
|
|
ia64_fph_enable();
|
|
__ia64_init_fpu();
|
|
ia64_fph_disable();
|
|
}
|
|
|
|
/* save f32-f127 at FPH */
|
|
static inline void
|
|
ia64_save_fpu (struct ia64_fpreg *fph) {
|
|
ia64_fph_enable();
|
|
__ia64_save_fpu(fph);
|
|
ia64_fph_disable();
|
|
}
|
|
|
|
/* load f32-f127 from FPH */
|
|
static inline void
|
|
ia64_load_fpu (struct ia64_fpreg *fph) {
|
|
ia64_fph_enable();
|
|
__ia64_load_fpu(fph);
|
|
ia64_fph_disable();
|
|
}
|
|
|
|
static inline __u64
|
|
ia64_clear_ic (void)
|
|
{
|
|
__u64 psr;
|
|
psr = ia64_getreg(_IA64_REG_PSR);
|
|
ia64_stop();
|
|
ia64_rsm(IA64_PSR_I | IA64_PSR_IC);
|
|
ia64_srlz_i();
|
|
return psr;
|
|
}
|
|
|
|
/*
|
|
* Restore the psr.
|
|
*/
|
|
static inline void
|
|
ia64_set_psr (__u64 psr)
|
|
{
|
|
ia64_stop();
|
|
ia64_setreg(_IA64_REG_PSR_L, psr);
|
|
ia64_srlz_d();
|
|
}
|
|
|
|
/*
|
|
* Insert a translation into an instruction and/or data translation
|
|
* register.
|
|
*/
|
|
static inline void
|
|
ia64_itr (__u64 target_mask, __u64 tr_num,
|
|
__u64 vmaddr, __u64 pte,
|
|
__u64 log_page_size)
|
|
{
|
|
ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
|
|
ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
|
|
ia64_stop();
|
|
if (target_mask & 0x1)
|
|
ia64_itri(tr_num, pte);
|
|
if (target_mask & 0x2)
|
|
ia64_itrd(tr_num, pte);
|
|
}
|
|
|
|
/*
|
|
* Insert a translation into the instruction and/or data translation
|
|
* cache.
|
|
*/
|
|
static inline void
|
|
ia64_itc (__u64 target_mask, __u64 vmaddr, __u64 pte,
|
|
__u64 log_page_size)
|
|
{
|
|
ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
|
|
ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
|
|
ia64_stop();
|
|
/* as per EAS2.6, itc must be the last instruction in an instruction group */
|
|
if (target_mask & 0x1)
|
|
ia64_itci(pte);
|
|
if (target_mask & 0x2)
|
|
ia64_itcd(pte);
|
|
}
|
|
|
|
/*
|
|
* Purge a range of addresses from instruction and/or data translation
|
|
* register(s).
|
|
*/
|
|
static inline void
|
|
ia64_ptr (__u64 target_mask, __u64 vmaddr, __u64 log_size)
|
|
{
|
|
if (target_mask & 0x1)
|
|
ia64_ptri(vmaddr, (log_size << 2));
|
|
if (target_mask & 0x2)
|
|
ia64_ptrd(vmaddr, (log_size << 2));
|
|
}
|
|
|
|
/* Set the interrupt vector address. The address must be suitably aligned (32KB). */
|
|
static inline void
|
|
ia64_set_iva (void *ivt_addr)
|
|
{
|
|
ia64_setreg(_IA64_REG_CR_IVA, (__u64) ivt_addr);
|
|
ia64_srlz_i();
|
|
}
|
|
|
|
/* Set the page table address and control bits. */
|
|
static inline void
|
|
ia64_set_pta (__u64 pta)
|
|
{
|
|
/* Note: srlz.i implies srlz.d */
|
|
ia64_setreg(_IA64_REG_CR_PTA, pta);
|
|
ia64_srlz_i();
|
|
}
|
|
|
|
static inline void
|
|
ia64_eoi (void)
|
|
{
|
|
ia64_setreg(_IA64_REG_CR_EOI, 0);
|
|
ia64_srlz_d();
|
|
}
|
|
|
|
#define cpu_relax() ia64_hint(ia64_hint_pause)
|
|
|
|
static inline int
|
|
ia64_get_irr(unsigned int vector)
|
|
{
|
|
unsigned int reg = vector / 64;
|
|
unsigned int bit = vector % 64;
|
|
u64 irr;
|
|
|
|
switch (reg) {
|
|
case 0: irr = ia64_getreg(_IA64_REG_CR_IRR0); break;
|
|
case 1: irr = ia64_getreg(_IA64_REG_CR_IRR1); break;
|
|
case 2: irr = ia64_getreg(_IA64_REG_CR_IRR2); break;
|
|
case 3: irr = ia64_getreg(_IA64_REG_CR_IRR3); break;
|
|
}
|
|
|
|
return test_bit(bit, &irr);
|
|
}
|
|
|
|
static inline void
|
|
ia64_set_lrr0 (unsigned long val)
|
|
{
|
|
ia64_setreg(_IA64_REG_CR_LRR0, val);
|
|
ia64_srlz_d();
|
|
}
|
|
|
|
static inline void
|
|
ia64_set_lrr1 (unsigned long val)
|
|
{
|
|
ia64_setreg(_IA64_REG_CR_LRR1, val);
|
|
ia64_srlz_d();
|
|
}
|
|
|
|
|
|
/*
|
|
* Given the address to which a spill occurred, return the unat bit
|
|
* number that corresponds to this address.
|
|
*/
|
|
static inline __u64
|
|
ia64_unat_pos (void *spill_addr)
|
|
{
|
|
return ((__u64) spill_addr >> 3) & 0x3f;
|
|
}
|
|
|
|
/*
|
|
* Set the NaT bit of an integer register which was spilled at address
|
|
* SPILL_ADDR. UNAT is the mask to be updated.
|
|
*/
|
|
static inline void
|
|
ia64_set_unat (__u64 *unat, void *spill_addr, unsigned long nat)
|
|
{
|
|
__u64 bit = ia64_unat_pos(spill_addr);
|
|
__u64 mask = 1UL << bit;
|
|
|
|
*unat = (*unat & ~mask) | (nat << bit);
|
|
}
|
|
|
|
/*
|
|
* Return saved PC of a blocked thread.
|
|
* Note that the only way T can block is through a call to schedule() -> switch_to().
|
|
*/
|
|
static inline unsigned long
|
|
thread_saved_pc (struct task_struct *t)
|
|
{
|
|
struct unw_frame_info info;
|
|
unsigned long ip;
|
|
|
|
unw_init_from_blocked_task(&info, t);
|
|
if (unw_unwind(&info) < 0)
|
|
return 0;
|
|
unw_get_ip(&info, &ip);
|
|
return ip;
|
|
}
|
|
|
|
/*
|
|
* Get the current instruction/program counter value.
|
|
*/
|
|
#define current_text_addr() \
|
|
({ void *_pc; _pc = (void *)ia64_getreg(_IA64_REG_IP); _pc; })
|
|
|
|
static inline __u64
|
|
ia64_get_ivr (void)
|
|
{
|
|
__u64 r;
|
|
ia64_srlz_d();
|
|
r = ia64_getreg(_IA64_REG_CR_IVR);
|
|
ia64_srlz_d();
|
|
return r;
|
|
}
|
|
|
|
static inline void
|
|
ia64_set_dbr (__u64 regnum, __u64 value)
|
|
{
|
|
__ia64_set_dbr(regnum, value);
|
|
#ifdef CONFIG_ITANIUM
|
|
ia64_srlz_d();
|
|
#endif
|
|
}
|
|
|
|
static inline __u64
|
|
ia64_get_dbr (__u64 regnum)
|
|
{
|
|
__u64 retval;
|
|
|
|
retval = __ia64_get_dbr(regnum);
|
|
#ifdef CONFIG_ITANIUM
|
|
ia64_srlz_d();
|
|
#endif
|
|
return retval;
|
|
}
|
|
|
|
static inline __u64
|
|
ia64_rotr (__u64 w, __u64 n)
|
|
{
|
|
return (w >> n) | (w << (64 - n));
|
|
}
|
|
|
|
#define ia64_rotl(w,n) ia64_rotr((w), (64) - (n))
|
|
|
|
/*
|
|
* Take a mapped kernel address and return the equivalent address
|
|
* in the region 7 identity mapped virtual area.
|
|
*/
|
|
static inline void *
|
|
ia64_imva (void *addr)
|
|
{
|
|
void *result;
|
|
result = (void *) ia64_tpa(addr);
|
|
return __va(result);
|
|
}
|
|
|
|
#define ARCH_HAS_PREFETCH
|
|
#define ARCH_HAS_PREFETCHW
|
|
#define ARCH_HAS_SPINLOCK_PREFETCH
|
|
#define PREFETCH_STRIDE L1_CACHE_BYTES
|
|
|
|
static inline void
|
|
prefetch (const void *x)
|
|
{
|
|
ia64_lfetch(ia64_lfhint_none, x);
|
|
}
|
|
|
|
static inline void
|
|
prefetchw (const void *x)
|
|
{
|
|
ia64_lfetch_excl(ia64_lfhint_none, x);
|
|
}
|
|
|
|
#define spin_lock_prefetch(x) prefetchw(x)
|
|
|
|
extern unsigned long boot_option_idle_override;
|
|
|
|
#endif /* !__ASSEMBLY__ */
|
|
|
|
#endif /* _ASM_IA64_PROCESSOR_H */
|