linux_dsm_epyc7002/drivers/clk/imx
Emil Lundmark c5a8045a55 clk: imx: improve precision of AV PLL to 1 Hz
The audio and video PLLs are designed to have a precision of 1 Hz if some
conditions are met. The current implementation only allows a precision that
depends on the rate of the parent clock. E.g., if the parent clock is 24
MHz, the precision will be 24 Hz; or more generally the precision will be

    p / 10^6 Hz

where p is the parent clock rate. This comes down to how the register
values for the PLL's fractional loop divider are chosen.

The clock rate calculation for the PLL is

    PLL output frequency = Fref * (DIV_SELECT + NUM / DENOM)

or with a shorter notation

    r = p * (d + a / b)

In addition to all variables being integers, we also have the following
conditions:

    27 <= d <= 54

    -2^29 <= a <= 2^29-1
     0    <  b <= 2^30-1
    |a| < b

Here, d, a and b are register values for the fractional loop divider. We
want to chose d, a and b such that f(p, r) = p, i.e. f is our round_rate
function. Currently, d and b are chosen as

    d = r / p
    b = 10^6

hence we get the poor precision. And a is defined in terms of r, d, p and
b:

    a = (r - d * p) * b / p

I propose that if p <= 2^30-1 (i.e., the max value for b), we chose b as

    b = p

We can do this since

    |a| < b

    |(r - d * p) * b / p| < b

    |r - d * p| < p

Which have two solutions, one of them is when p < 0, so we can skip that
one. The other is when p > 0 and

    p * (d - 1) < r < p * (d + 1)

Substitute d = r / p:

    (r - p) < r < (r + p)  <=>  p > 0

So, as long as p > 0, we can chose b = p. This is a good choise for b since

    a = (r - d * p) * b / p
      = (r - d * p) * p / p
      = r - d * p

    r = p * (d + a / b)
      = p * d + p * a / b
      = p * d + p * a / p
      = p * d + a

and if d = r / p:

    a = r - d * p
      = r - r / p * p
      = 0

    r = p * d + a
      = p * d + 0
      = p * r / p
      = r

I reckon this is the intention by the design of the clock rate formula.

Signed-off-by: Emil Lundmark <emil@limesaudio.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-01 17:12:50 -07:00
..
clk-busy.c clk: move the common clock's to_clk_*(_hw) macros to clk-provider.h 2016-01-29 12:59:50 -08:00
clk-cpu.c
clk-fixup-div.c clk: move the common clock's to_clk_*(_hw) macros to clk-provider.h 2016-01-29 12:59:50 -08:00
clk-fixup-mux.c clk: move the common clock's to_clk_*(_hw) macros to clk-provider.h 2016-01-29 12:59:50 -08:00
clk-gate2.c clk: imx: clk-gate2: allow custom gate configuration 2016-03-31 17:01:55 +08:00
clk-gate-exclusive.c clk: move the common clock's to_clk_*(_hw) macros to clk-provider.h 2016-01-29 12:59:50 -08:00
clk-imx1.c ARM: i.MX: Remove i.MX1 non-DT support 2016-08-09 22:47:26 +08:00
clk-imx6q.c clk: imx6: initialize GPU clocks 2016-09-20 16:57:15 -07:00
clk-imx6sl.c clk: imx: fix pll clock parents 2016-06-12 21:21:41 +08:00
clk-imx6sx.c clk: imx: fix pll clock parents 2016-06-12 21:21:41 +08:00
clk-imx6ul.c clk: imx6ul: fix gpt2 clock names 2016-06-16 09:05:55 +08:00
clk-imx7d.c clk: imx7d: Add PLL_AUDIO_TEST_DIV/POST_DIV clocks 2016-08-30 14:58:15 -07:00
clk-imx21.c
clk-imx25.c clk: imx25: Remove osc clock from driver 2015-11-25 11:49:42 +08:00
clk-imx27.c
clk-imx31.c clk: imx31: add missing of_node_put 2015-10-21 16:16:34 -07:00
clk-imx35.c ARM: clk-imx35: annotate clk enum with number values 2016-09-14 11:28:04 -07:00
clk-imx51-imx53.c clk: imx53: Add clocks configuration 2016-09-20 16:52:06 -07:00
clk-pfd.c
clk-pllv1.c imx/clk-pllv1: fix wrong do_div() usage 2015-11-30 12:58:35 -08:00
clk-pllv2.c imx/clk-pllv2: fix wrong do_div() usage 2015-11-30 12:58:38 -08:00
clk-pllv3.c clk: imx: improve precision of AV PLL to 1 Hz 2016-11-01 17:12:50 -07:00
clk-vf610.c clk: imx: vf610: Disable automatic clock gating for lpuart in LPSTOP mode 2016-07-08 11:38:17 -07:00
clk.c
clk.h clk: imx: Introduce clk_register_gate2() 2016-08-19 12:53:41 -07:00
Makefile