Aapo Vienamo 57d1654ec9 mmc: tegra: Force correct divider calculation on DDR50/52 ... Tegra SDHCI controllers require the SDHCI clock divider to be configured to divide the clock by two in DDR50/52 modes. Incorrectly configured clock divider results in corrupted data. Prevent the possibility of incorrectly calculating the divider value due to clock rate rounding or low parent clock frequency by not assigning host->max_clk to clk_get_rate() on tegra_sdhci_set_clock(). See the comments for further details. Fixes: a8e326a ("mmc: tegra: implement module external clock change") Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>		2018-07-30 15:06:31 +02:00
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core	mmc: core: Drop the unused mmc_power_save|restore_host()	2018-07-16 11:21:45 +02:00
host	mmc: tegra: Force correct divider calculation on DDR50/52	2018-07-30 15:06:31 +02:00
Kconfig	mmc: core: Remove option not to use blk-mq	2017-12-11 12:55:02 +01:00
Makefile	mmc: Kconfig: downgrade CONFIG_MMC_DEBUG for host drivers only	2017-08-30 14:01:34 +02:00