mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 21:47:04 +07:00
f61990f3c5
This flag is a no-op now. Remove usage of the flag. Tested-by: Leo Yan <leo.yan@linaro.org> Cc: Bintian Wang <bintian.wang@huawei.com> Cc: Zhangfei Gao <zhangfei.gao@linaro.org> Cc: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
57 lines
1.7 KiB
C
57 lines
1.7 KiB
C
/*
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* Hisilicon HiP04 clock driver
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*
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* Copyright (c) 2013-2014 Hisilicon Limited.
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* Copyright (c) 2013-2014 Linaro Limited.
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*
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* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/slab.h>
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#include <dt-bindings/clock/hip04-clock.h>
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#include "clk.h"
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/* fixed rate clocks */
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static struct hisi_fixed_rate_clock hip04_fixed_rate_clks[] __initdata = {
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{ HIP04_OSC50M, "osc50m", NULL, 0, 50000000, },
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{ HIP04_CLK_50M, "clk50m", NULL, 0, 50000000, },
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{ HIP04_CLK_168M, "clk168m", NULL, 0, 168750000, },
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};
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static void __init hip04_clk_init(struct device_node *np)
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{
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struct hisi_clock_data *clk_data;
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clk_data = hisi_clk_init(np, HIP04_NR_CLKS);
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if (!clk_data)
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return;
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hisi_clk_register_fixed_rate(hip04_fixed_rate_clks,
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ARRAY_SIZE(hip04_fixed_rate_clks),
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clk_data);
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}
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CLK_OF_DECLARE(hip04_clk, "hisilicon,hip04-clock", hip04_clk_init);
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