Kisoo Yu 57b317f912 ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll ... The fout clock of BPLL and MPLL have a selectable source on EXYNOS5250. The clock options are a fixed divided by 2 clock and the output of the PLL itself. Add support for these new clock instances. Signed-off-by: Kisoo Yu <ksoo.yu@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> [kgene.kim@samsung.com: moved common pll stuff into s5p-clock.c] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>		2012-05-16 07:03:41 +09:00
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plat	ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll	2012-05-16 07:03:41 +09:00