mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 09:02:57 +07:00
410feb75de
- Spectre v4 mitigation (Speculative Store Bypass Disable) support for arm64 using SMC firmware call to set a hardware chicken bit - ACPI PPTT (Processor Properties Topology Table) parsing support and enable the feature for arm64 - Report signal frame size to user via auxv (AT_MINSIGSTKSZ). The primary motivation is Scalable Vector Extensions which requires more space on the signal frame than the currently defined MINSIGSTKSZ - ARM perf patches: allow building arm-cci as module, demote dev_warn() to dev_dbg() in arm-ccn event_init(), miscellaneous cleanups - cmpwait() WFE optimisation to avoid some spurious wakeups - L1_CACHE_BYTES reverted back to 64 (for performance reasons that have to do with some network allocations) while keeping ARCH_DMA_MINALIGN to 128. cache_line_size() returns the actual hardware Cache Writeback Granule - Turn LSE atomics on by default in Kconfig - Kernel fault reporting tidying - Some #include and miscellaneous cleanups -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE5RElWfyWxS+3PLO2a9axLQDIXvEFAlsaoqsACgkQa9axLQDI XvH+8RAAqRCrEtkNPS7zxHyMK/D2cxSy9EVtlJ1sxhmsONEe5t5MDTWX9byobQ5A PAKMSQBQgUvecqHLOtD7SJWef1il30zgWmc/yPcgNv3OsA1Au7j2g3ht/Drw+N5I Vy0aOUEtw+Jzs7y/CJyl6lufSkkOzszOujt2Nybiz6omztOrwkW9isKnURzQBNj5 gquZI35h604YJ9F0TqS6ZqU7tNcuB9q02FxvVBpLmb83jP4jSEjYACUJwVVxvEAB UXjdD4N130rRXDS5OMRWo5+4SAj+kPYhdVYEvaDx7xTOIRHhXK05GlJbsUAc5E6l xy810fH5Dm0diYpVvYWTA5J+BU1jNOvCys5zKWl7gs2P8YB59PdqY4M2YBPNGb5H PaVgq73TZAsww6ZInbZlK+wZOIxZZIOf//Z+QKn6EPtu3RmzIFWwyttTj01w1E3i LhjcUoGnvxJFcMoCr59ihDwfP9nkCVrNc4REOGaWDk6L/t/bOfaZfDz+OCGbwQdL akCFKZI6q5O/no+YfhtdtNFpCQb/Bo1J88KuotICRXq8z4vO41zIG53bi97W8QeG rCBiX0NxUxYJ3ybus7kZHTmMGieMyEHP28n12QffwvJj4vJBsUXQBrV8hclx0djZ HMt7iPi/0BW6nVV7ngIgN3cdCpaDCEGRsfO4Ch0rFZrC9UbYQnE= =uums -----END PGP SIGNATURE----- Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 updates from Catalin Marinas: "Apart from the core arm64 and perf changes, the Spectre v4 mitigation touches the arm KVM code and the ACPI PPTT support touches drivers/ (acpi and cacheinfo). I should have the maintainers' acks in place. Summary: - Spectre v4 mitigation (Speculative Store Bypass Disable) support for arm64 using SMC firmware call to set a hardware chicken bit - ACPI PPTT (Processor Properties Topology Table) parsing support and enable the feature for arm64 - Report signal frame size to user via auxv (AT_MINSIGSTKSZ). The primary motivation is Scalable Vector Extensions which requires more space on the signal frame than the currently defined MINSIGSTKSZ - ARM perf patches: allow building arm-cci as module, demote dev_warn() to dev_dbg() in arm-ccn event_init(), miscellaneous cleanups - cmpwait() WFE optimisation to avoid some spurious wakeups - L1_CACHE_BYTES reverted back to 64 (for performance reasons that have to do with some network allocations) while keeping ARCH_DMA_MINALIGN to 128. cache_line_size() returns the actual hardware Cache Writeback Granule - Turn LSE atomics on by default in Kconfig - Kernel fault reporting tidying - Some #include and miscellaneous cleanups" * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (53 commits) arm64: Fix syscall restarting around signal suppressed by tracer arm64: topology: Avoid checking numa mask for scheduler MC selection ACPI / PPTT: fix build when CONFIG_ACPI_PPTT is not enabled arm64: cpu_errata: include required headers arm64: KVM: Move VCPU_WORKAROUND_2_FLAG macros to the top of the file arm64: signal: Report signal frame size to userspace via auxv arm64/sve: Thin out initialisation sanity-checks for sve_max_vl arm64: KVM: Add ARCH_WORKAROUND_2 discovery through ARCH_FEATURES_FUNC_ID arm64: KVM: Handle guest's ARCH_WORKAROUND_2 requests arm64: KVM: Add ARCH_WORKAROUND_2 support for guests arm64: KVM: Add HYP per-cpu accessors arm64: ssbd: Add prctl interface for per-thread mitigation arm64: ssbd: Introduce thread flag to control userspace mitigation arm64: ssbd: Restore mitigation status on CPU resume arm64: ssbd: Skip apply_ssbd if not using dynamic mitigation arm64: ssbd: Add global mitigation state accessor arm64: Add 'ssbd' command-line option arm64: Add ARCH_WORKAROUND_2 probing arm64: Add per-cpu infrastructure to call ARCH_WORKAROUND_2 arm64: Call ARCH_WORKAROUND_2 on transitions between EL0 and EL1 ...
676 lines
17 KiB
C
676 lines
17 KiB
C
/*
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* Contains CPU specific errata definitions
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*
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* Copyright (C) 2014 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/arm-smccc.h>
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#include <linux/psci.h>
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#include <linux/types.h>
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#include <asm/cpu.h>
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#include <asm/cputype.h>
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#include <asm/cpufeature.h>
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static bool __maybe_unused
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is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
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{
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const struct arm64_midr_revidr *fix;
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u32 midr = read_cpuid_id(), revidr;
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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if (!is_midr_in_range(midr, &entry->midr_range))
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return false;
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midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
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revidr = read_cpuid(REVIDR_EL1);
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for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
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if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
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return false;
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return true;
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}
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static bool __maybe_unused
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is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,
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int scope)
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{
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
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}
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static bool __maybe_unused
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is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
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{
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u32 model;
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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model = read_cpuid_id();
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model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
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MIDR_ARCHITECTURE_MASK;
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return model == entry->midr_range.model;
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}
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static bool
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has_mismatched_cache_line_size(const struct arm64_cpu_capabilities *entry,
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int scope)
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{
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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return (read_cpuid_cachetype() & arm64_ftr_reg_ctrel0.strict_mask) !=
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(arm64_ftr_reg_ctrel0.sys_val & arm64_ftr_reg_ctrel0.strict_mask);
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}
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static void
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cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *__unused)
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{
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/* Clear SCTLR_EL1.UCT */
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config_sctlr_el1(SCTLR_EL1_UCT, 0);
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}
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atomic_t arm64_el2_vector_last_slot = ATOMIC_INIT(-1);
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#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
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#include <asm/mmu_context.h>
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#include <asm/cacheflush.h>
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DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);
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#ifdef CONFIG_KVM_INDIRECT_VECTORS
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extern char __smccc_workaround_1_smc_start[];
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extern char __smccc_workaround_1_smc_end[];
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static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start,
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const char *hyp_vecs_end)
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{
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void *dst = lm_alias(__bp_harden_hyp_vecs_start + slot * SZ_2K);
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int i;
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for (i = 0; i < SZ_2K; i += 0x80)
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memcpy(dst + i, hyp_vecs_start, hyp_vecs_end - hyp_vecs_start);
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flush_icache_range((uintptr_t)dst, (uintptr_t)dst + SZ_2K);
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}
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static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
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const char *hyp_vecs_start,
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const char *hyp_vecs_end)
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{
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static DEFINE_SPINLOCK(bp_lock);
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int cpu, slot = -1;
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spin_lock(&bp_lock);
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for_each_possible_cpu(cpu) {
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if (per_cpu(bp_hardening_data.fn, cpu) == fn) {
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slot = per_cpu(bp_hardening_data.hyp_vectors_slot, cpu);
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break;
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}
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}
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if (slot == -1) {
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slot = atomic_inc_return(&arm64_el2_vector_last_slot);
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BUG_ON(slot >= BP_HARDEN_EL2_SLOTS);
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__copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end);
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}
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__this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot);
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__this_cpu_write(bp_hardening_data.fn, fn);
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spin_unlock(&bp_lock);
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}
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#else
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#define __smccc_workaround_1_smc_start NULL
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#define __smccc_workaround_1_smc_end NULL
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static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
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const char *hyp_vecs_start,
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const char *hyp_vecs_end)
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{
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__this_cpu_write(bp_hardening_data.fn, fn);
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}
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#endif /* CONFIG_KVM_INDIRECT_VECTORS */
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static void install_bp_hardening_cb(const struct arm64_cpu_capabilities *entry,
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bp_hardening_cb_t fn,
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const char *hyp_vecs_start,
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const char *hyp_vecs_end)
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{
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u64 pfr0;
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if (!entry->matches(entry, SCOPE_LOCAL_CPU))
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return;
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pfr0 = read_cpuid(ID_AA64PFR0_EL1);
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if (cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_CSV2_SHIFT))
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return;
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__install_bp_hardening_cb(fn, hyp_vecs_start, hyp_vecs_end);
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}
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#include <uapi/linux/psci.h>
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#include <linux/arm-smccc.h>
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#include <linux/psci.h>
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static void call_smc_arch_workaround_1(void)
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{
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arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
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}
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static void call_hvc_arch_workaround_1(void)
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{
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arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
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}
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static void qcom_link_stack_sanitization(void)
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{
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u64 tmp;
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asm volatile("mov %0, x30 \n"
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".rept 16 \n"
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"bl . + 4 \n"
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".endr \n"
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"mov x30, %0 \n"
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: "=&r" (tmp));
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}
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static void
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enable_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry)
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{
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bp_hardening_cb_t cb;
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void *smccc_start, *smccc_end;
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struct arm_smccc_res res;
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u32 midr = read_cpuid_id();
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if (!entry->matches(entry, SCOPE_LOCAL_CPU))
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return;
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if (psci_ops.smccc_version == SMCCC_VERSION_1_0)
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return;
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switch (psci_ops.conduit) {
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case PSCI_CONDUIT_HVC:
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arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
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ARM_SMCCC_ARCH_WORKAROUND_1, &res);
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if ((int)res.a0 < 0)
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return;
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cb = call_hvc_arch_workaround_1;
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/* This is a guest, no need to patch KVM vectors */
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smccc_start = NULL;
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smccc_end = NULL;
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break;
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case PSCI_CONDUIT_SMC:
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arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
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ARM_SMCCC_ARCH_WORKAROUND_1, &res);
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if ((int)res.a0 < 0)
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return;
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cb = call_smc_arch_workaround_1;
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smccc_start = __smccc_workaround_1_smc_start;
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smccc_end = __smccc_workaround_1_smc_end;
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break;
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default:
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return;
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}
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if (((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR) ||
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((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1))
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cb = qcom_link_stack_sanitization;
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install_bp_hardening_cb(entry, cb, smccc_start, smccc_end);
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return;
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}
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#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */
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#ifdef CONFIG_ARM64_SSBD
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DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required);
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int ssbd_state __read_mostly = ARM64_SSBD_KERNEL;
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static const struct ssbd_options {
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const char *str;
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int state;
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} ssbd_options[] = {
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{ "force-on", ARM64_SSBD_FORCE_ENABLE, },
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{ "force-off", ARM64_SSBD_FORCE_DISABLE, },
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{ "kernel", ARM64_SSBD_KERNEL, },
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};
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static int __init ssbd_cfg(char *buf)
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{
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int i;
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if (!buf || !buf[0])
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return -EINVAL;
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for (i = 0; i < ARRAY_SIZE(ssbd_options); i++) {
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int len = strlen(ssbd_options[i].str);
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if (strncmp(buf, ssbd_options[i].str, len))
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continue;
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ssbd_state = ssbd_options[i].state;
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return 0;
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}
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return -EINVAL;
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}
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early_param("ssbd", ssbd_cfg);
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void __init arm64_update_smccc_conduit(struct alt_instr *alt,
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__le32 *origptr, __le32 *updptr,
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int nr_inst)
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{
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u32 insn;
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BUG_ON(nr_inst != 1);
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switch (psci_ops.conduit) {
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case PSCI_CONDUIT_HVC:
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insn = aarch64_insn_get_hvc_value();
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break;
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case PSCI_CONDUIT_SMC:
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insn = aarch64_insn_get_smc_value();
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break;
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default:
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return;
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}
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*updptr = cpu_to_le32(insn);
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}
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void __init arm64_enable_wa2_handling(struct alt_instr *alt,
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__le32 *origptr, __le32 *updptr,
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int nr_inst)
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{
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BUG_ON(nr_inst != 1);
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/*
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* Only allow mitigation on EL1 entry/exit and guest
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* ARCH_WORKAROUND_2 handling if the SSBD state allows it to
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* be flipped.
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*/
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if (arm64_get_ssbd_state() == ARM64_SSBD_KERNEL)
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*updptr = cpu_to_le32(aarch64_insn_gen_nop());
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}
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void arm64_set_ssbd_mitigation(bool state)
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{
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switch (psci_ops.conduit) {
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case PSCI_CONDUIT_HVC:
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arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_2, state, NULL);
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break;
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case PSCI_CONDUIT_SMC:
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arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2, state, NULL);
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break;
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default:
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WARN_ON_ONCE(1);
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break;
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}
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}
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static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry,
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int scope)
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{
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struct arm_smccc_res res;
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bool required = true;
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s32 val;
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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if (psci_ops.smccc_version == SMCCC_VERSION_1_0) {
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ssbd_state = ARM64_SSBD_UNKNOWN;
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return false;
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}
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switch (psci_ops.conduit) {
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case PSCI_CONDUIT_HVC:
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arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
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ARM_SMCCC_ARCH_WORKAROUND_2, &res);
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break;
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case PSCI_CONDUIT_SMC:
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arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
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ARM_SMCCC_ARCH_WORKAROUND_2, &res);
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break;
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default:
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ssbd_state = ARM64_SSBD_UNKNOWN;
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return false;
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}
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val = (s32)res.a0;
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switch (val) {
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case SMCCC_RET_NOT_SUPPORTED:
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ssbd_state = ARM64_SSBD_UNKNOWN;
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return false;
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case SMCCC_RET_NOT_REQUIRED:
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pr_info_once("%s mitigation not required\n", entry->desc);
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ssbd_state = ARM64_SSBD_MITIGATED;
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return false;
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case SMCCC_RET_SUCCESS:
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required = true;
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break;
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case 1: /* Mitigation not required on this CPU */
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required = false;
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break;
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default:
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WARN_ON(1);
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return false;
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}
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switch (ssbd_state) {
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case ARM64_SSBD_FORCE_DISABLE:
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pr_info_once("%s disabled from command-line\n", entry->desc);
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arm64_set_ssbd_mitigation(false);
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required = false;
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break;
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case ARM64_SSBD_KERNEL:
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if (required) {
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__this_cpu_write(arm64_ssbd_callback_required, 1);
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arm64_set_ssbd_mitigation(true);
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}
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break;
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case ARM64_SSBD_FORCE_ENABLE:
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pr_info_once("%s forced from command-line\n", entry->desc);
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arm64_set_ssbd_mitigation(true);
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required = true;
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break;
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default:
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WARN_ON(1);
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break;
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}
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return required;
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}
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#endif /* CONFIG_ARM64_SSBD */
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#define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
|
|
.matches = is_affected_midr_range, \
|
|
.midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)
|
|
|
|
#define CAP_MIDR_ALL_VERSIONS(model) \
|
|
.matches = is_affected_midr_range, \
|
|
.midr_range = MIDR_ALL_VERSIONS(model)
|
|
|
|
#define MIDR_FIXED(rev, revidr_mask) \
|
|
.fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
|
|
|
|
#define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
|
|
CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
|
|
|
|
#define CAP_MIDR_RANGE_LIST(list) \
|
|
.matches = is_affected_midr_range_list, \
|
|
.midr_range_list = list
|
|
|
|
/* Errata affecting a range of revisions of given model variant */
|
|
#define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \
|
|
ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
|
|
|
|
/* Errata affecting a single variant/revision of a model */
|
|
#define ERRATA_MIDR_REV(model, var, rev) \
|
|
ERRATA_MIDR_RANGE(model, var, rev, var, rev)
|
|
|
|
/* Errata affecting all variants/revisions of a given a model */
|
|
#define ERRATA_MIDR_ALL_VERSIONS(model) \
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
|
|
CAP_MIDR_ALL_VERSIONS(model)
|
|
|
|
/* Errata affecting a list of midr ranges, with same work around */
|
|
#define ERRATA_MIDR_RANGE_LIST(midr_list) \
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \
|
|
CAP_MIDR_RANGE_LIST(midr_list)
|
|
|
|
/*
|
|
* Generic helper for handling capabilties with multiple (match,enable) pairs
|
|
* of call backs, sharing the same capability bit.
|
|
* Iterate over each entry to see if at least one matches.
|
|
*/
|
|
static bool __maybe_unused
|
|
multi_entry_cap_matches(const struct arm64_cpu_capabilities *entry, int scope)
|
|
{
|
|
const struct arm64_cpu_capabilities *caps;
|
|
|
|
for (caps = entry->match_list; caps->matches; caps++)
|
|
if (caps->matches(caps, scope))
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
/*
|
|
* Take appropriate action for all matching entries in the shared capability
|
|
* entry.
|
|
*/
|
|
static void __maybe_unused
|
|
multi_entry_cap_cpu_enable(const struct arm64_cpu_capabilities *entry)
|
|
{
|
|
const struct arm64_cpu_capabilities *caps;
|
|
|
|
for (caps = entry->match_list; caps->matches; caps++)
|
|
if (caps->matches(caps, SCOPE_LOCAL_CPU) &&
|
|
caps->cpu_enable)
|
|
caps->cpu_enable(caps);
|
|
}
|
|
|
|
#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
|
|
|
|
/*
|
|
* List of CPUs where we need to issue a psci call to
|
|
* harden the branch predictor.
|
|
*/
|
|
static const struct midr_range arm64_bp_harden_smccc_cpus[] = {
|
|
MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
|
|
MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
|
|
MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
|
|
MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
|
|
MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
|
|
MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
|
|
MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
|
|
MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
|
|
MIDR_ALL_VERSIONS(MIDR_NVIDIA_DENVER),
|
|
{},
|
|
};
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_HARDEN_EL2_VECTORS
|
|
|
|
static const struct midr_range arm64_harden_el2_vectors[] = {
|
|
MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
|
|
MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
|
|
{},
|
|
};
|
|
|
|
#endif
|
|
|
|
const struct arm64_cpu_capabilities arm64_errata[] = {
|
|
#if defined(CONFIG_ARM64_ERRATUM_826319) || \
|
|
defined(CONFIG_ARM64_ERRATUM_827319) || \
|
|
defined(CONFIG_ARM64_ERRATUM_824069)
|
|
{
|
|
/* Cortex-A53 r0p[012] */
|
|
.desc = "ARM errata 826319, 827319, 824069",
|
|
.capability = ARM64_WORKAROUND_CLEAN_CACHE,
|
|
ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
|
|
.cpu_enable = cpu_enable_cache_maint_trap,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_819472
|
|
{
|
|
/* Cortex-A53 r0p[01] */
|
|
.desc = "ARM errata 819472",
|
|
.capability = ARM64_WORKAROUND_CLEAN_CACHE,
|
|
ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
|
|
.cpu_enable = cpu_enable_cache_maint_trap,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_832075
|
|
{
|
|
/* Cortex-A57 r0p0 - r1p2 */
|
|
.desc = "ARM erratum 832075",
|
|
.capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
|
|
ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
|
|
0, 0,
|
|
1, 2),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_834220
|
|
{
|
|
/* Cortex-A57 r0p0 - r1p2 */
|
|
.desc = "ARM erratum 834220",
|
|
.capability = ARM64_WORKAROUND_834220,
|
|
ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
|
|
0, 0,
|
|
1, 2),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_843419
|
|
{
|
|
/* Cortex-A53 r0p[01234] */
|
|
.desc = "ARM erratum 843419",
|
|
.capability = ARM64_WORKAROUND_843419,
|
|
ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
|
|
MIDR_FIXED(0x4, BIT(8)),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_845719
|
|
{
|
|
/* Cortex-A53 r0p[01234] */
|
|
.desc = "ARM erratum 845719",
|
|
.capability = ARM64_WORKAROUND_845719,
|
|
ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CAVIUM_ERRATUM_23154
|
|
{
|
|
/* Cavium ThunderX, pass 1.x */
|
|
.desc = "Cavium erratum 23154",
|
|
.capability = ARM64_WORKAROUND_CAVIUM_23154,
|
|
ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CAVIUM_ERRATUM_27456
|
|
{
|
|
/* Cavium ThunderX, T88 pass 1.x - 2.1 */
|
|
.desc = "Cavium erratum 27456",
|
|
.capability = ARM64_WORKAROUND_CAVIUM_27456,
|
|
ERRATA_MIDR_RANGE(MIDR_THUNDERX,
|
|
0, 0,
|
|
1, 1),
|
|
},
|
|
{
|
|
/* Cavium ThunderX, T81 pass 1.0 */
|
|
.desc = "Cavium erratum 27456",
|
|
.capability = ARM64_WORKAROUND_CAVIUM_27456,
|
|
ERRATA_MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_CAVIUM_ERRATUM_30115
|
|
{
|
|
/* Cavium ThunderX, T88 pass 1.x - 2.2 */
|
|
.desc = "Cavium erratum 30115",
|
|
.capability = ARM64_WORKAROUND_CAVIUM_30115,
|
|
ERRATA_MIDR_RANGE(MIDR_THUNDERX,
|
|
0, 0,
|
|
1, 2),
|
|
},
|
|
{
|
|
/* Cavium ThunderX, T81 pass 1.0 - 1.2 */
|
|
.desc = "Cavium erratum 30115",
|
|
.capability = ARM64_WORKAROUND_CAVIUM_30115,
|
|
ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),
|
|
},
|
|
{
|
|
/* Cavium ThunderX, T83 pass 1.0 */
|
|
.desc = "Cavium erratum 30115",
|
|
.capability = ARM64_WORKAROUND_CAVIUM_30115,
|
|
ERRATA_MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),
|
|
},
|
|
#endif
|
|
{
|
|
.desc = "Mismatched cache line size",
|
|
.capability = ARM64_MISMATCHED_CACHE_LINE_SIZE,
|
|
.matches = has_mismatched_cache_line_size,
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
|
.cpu_enable = cpu_enable_trap_ctr_access,
|
|
},
|
|
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
|
|
{
|
|
.desc = "Qualcomm Technologies Falkor erratum 1003",
|
|
.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
|
|
ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
|
|
},
|
|
{
|
|
.desc = "Qualcomm Technologies Kryo erratum 1003",
|
|
.capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
|
.midr_range.model = MIDR_QCOM_KRYO,
|
|
.matches = is_kryo_midr,
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
|
|
{
|
|
.desc = "Qualcomm Technologies Falkor erratum 1009",
|
|
.capability = ARM64_WORKAROUND_REPEAT_TLBI,
|
|
ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_ERRATUM_858921
|
|
{
|
|
/* Cortex-A73 all versions */
|
|
.desc = "ARM erratum 858921",
|
|
.capability = ARM64_WORKAROUND_858921,
|
|
ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
|
|
{
|
|
.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
|
.cpu_enable = enable_smccc_arch_workaround_1,
|
|
ERRATA_MIDR_RANGE_LIST(arm64_bp_harden_smccc_cpus),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_HARDEN_EL2_VECTORS
|
|
{
|
|
.desc = "EL2 vector hardening",
|
|
.capability = ARM64_HARDEN_EL2_VECTORS,
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
|
ERRATA_MIDR_RANGE_LIST(arm64_harden_el2_vectors),
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_ARM64_SSBD
|
|
{
|
|
.desc = "Speculative Store Bypass Disable",
|
|
.capability = ARM64_SSBD,
|
|
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
|
|
.matches = has_ssbd_mitigation,
|
|
},
|
|
#endif
|
|
{
|
|
}
|
|
};
|