mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 03:35:36 +07:00
04759194dc
- VMAP_STACK support, allowing the kernel stacks to be allocated in
the vmalloc space with a guard page for trapping stack overflows. One
of the patches introduces THREAD_ALIGN and changes the generic
alloc_thread_stack_node() to use this instead of THREAD_SIZE (no
functional change for other architectures)
- Contiguous PTE hugetlb support re-enabled (after being reverted a
couple of times). We now have the semantics agreed in the generic mm
layer together with API improvements so that the architecture code can
detect between contiguous and non-contiguous huge PTEs
- Initial support for persistent memory on ARM: DC CVAP instruction
exposed to user space (HWCAP) and the in-kernel pmem API implemented
- raid6 improvements for arm64: faster algorithm for the delta syndrome
and implementation of the recovery routines using Neon
- FP/SIMD refactoring and removal of support for Neon in interrupt
context. This is in preparation for full SVE support
- PTE accessors converted from inline asm to cmpxchg so that we can
use LSE atomics if available (ARMv8.1)
- Perf support for Cortex-A35 and A73
- Non-urgent fixes and cleanups
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Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 updates from Catalin Marinas:
- VMAP_STACK support, allowing the kernel stacks to be allocated in the
vmalloc space with a guard page for trapping stack overflows. One of
the patches introduces THREAD_ALIGN and changes the generic
alloc_thread_stack_node() to use this instead of THREAD_SIZE (no
functional change for other architectures)
- Contiguous PTE hugetlb support re-enabled (after being reverted a
couple of times). We now have the semantics agreed in the generic mm
layer together with API improvements so that the architecture code
can detect between contiguous and non-contiguous huge PTEs
- Initial support for persistent memory on ARM: DC CVAP instruction
exposed to user space (HWCAP) and the in-kernel pmem API implemented
- raid6 improvements for arm64: faster algorithm for the delta syndrome
and implementation of the recovery routines using Neon
- FP/SIMD refactoring and removal of support for Neon in interrupt
context. This is in preparation for full SVE support
- PTE accessors converted from inline asm to cmpxchg so that we can use
LSE atomics if available (ARMv8.1)
- Perf support for Cortex-A35 and A73
- Non-urgent fixes and cleanups
* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (75 commits)
arm64: cleanup {COMPAT_,}SET_PERSONALITY() macro
arm64: introduce separated bits for mm_context_t flags
arm64: hugetlb: Cleanup setup_hugepagesz
arm64: Re-enable support for contiguous hugepages
arm64: hugetlb: Override set_huge_swap_pte_at() to support contiguous hugepages
arm64: hugetlb: Override huge_pte_clear() to support contiguous hugepages
arm64: hugetlb: Handle swap entries in huge_pte_offset() for contiguous hugepages
arm64: hugetlb: Add break-before-make logic for contiguous entries
arm64: hugetlb: Spring clean huge pte accessors
arm64: hugetlb: Introduce pte_pgprot helper
arm64: hugetlb: set_huge_pte_at Add WARN_ON on !pte_present
arm64: kexec: have own crash_smp_send_stop() for crash dump for nonpanic cores
arm64: dma-mapping: Mark atomic_pool as __ro_after_init
arm64: dma-mapping: Do not pass data to gen_pool_set_algo()
arm64: Remove the !CONFIG_ARM64_HW_AFDBM alternative code paths
arm64: Ignore hardware dirty bit updates in ptep_set_wrprotect()
arm64: Move PTE_RDONLY bit handling out of set_pte_at()
kvm: arm64: Convert kvm_set_s2pte_readonly() from inline asm to cmpxchg()
arm64: Convert pte handling from inline asm to using (cmp)xchg
arm64: neon/efi: Make EFI fpsimd save/restore variables static
...
210 lines
5.7 KiB
C
210 lines
5.7 KiB
C
/*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_ELF_H
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#define __ASM_ELF_H
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#include <asm/hwcap.h>
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/*
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* ELF register definitions..
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*/
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#include <asm/ptrace.h>
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#include <asm/user.h>
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/*
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* AArch64 static relocation types.
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*/
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/* Miscellaneous. */
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#define R_ARM_NONE 0
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#define R_AARCH64_NONE 256
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/* Data. */
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#define R_AARCH64_ABS64 257
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#define R_AARCH64_ABS32 258
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#define R_AARCH64_ABS16 259
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#define R_AARCH64_PREL64 260
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#define R_AARCH64_PREL32 261
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#define R_AARCH64_PREL16 262
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/* Instructions. */
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#define R_AARCH64_MOVW_UABS_G0 263
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#define R_AARCH64_MOVW_UABS_G0_NC 264
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#define R_AARCH64_MOVW_UABS_G1 265
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#define R_AARCH64_MOVW_UABS_G1_NC 266
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#define R_AARCH64_MOVW_UABS_G2 267
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#define R_AARCH64_MOVW_UABS_G2_NC 268
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#define R_AARCH64_MOVW_UABS_G3 269
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#define R_AARCH64_MOVW_SABS_G0 270
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#define R_AARCH64_MOVW_SABS_G1 271
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#define R_AARCH64_MOVW_SABS_G2 272
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#define R_AARCH64_LD_PREL_LO19 273
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#define R_AARCH64_ADR_PREL_LO21 274
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#define R_AARCH64_ADR_PREL_PG_HI21 275
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#define R_AARCH64_ADR_PREL_PG_HI21_NC 276
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#define R_AARCH64_ADD_ABS_LO12_NC 277
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#define R_AARCH64_LDST8_ABS_LO12_NC 278
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#define R_AARCH64_TSTBR14 279
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#define R_AARCH64_CONDBR19 280
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#define R_AARCH64_JUMP26 282
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#define R_AARCH64_CALL26 283
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#define R_AARCH64_LDST16_ABS_LO12_NC 284
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#define R_AARCH64_LDST32_ABS_LO12_NC 285
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#define R_AARCH64_LDST64_ABS_LO12_NC 286
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#define R_AARCH64_LDST128_ABS_LO12_NC 299
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#define R_AARCH64_MOVW_PREL_G0 287
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#define R_AARCH64_MOVW_PREL_G0_NC 288
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#define R_AARCH64_MOVW_PREL_G1 289
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#define R_AARCH64_MOVW_PREL_G1_NC 290
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#define R_AARCH64_MOVW_PREL_G2 291
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#define R_AARCH64_MOVW_PREL_G2_NC 292
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#define R_AARCH64_MOVW_PREL_G3 293
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#define R_AARCH64_RELATIVE 1027
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/*
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* These are used to set parameters in the core dumps.
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*/
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#define ELF_CLASS ELFCLASS64
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#ifdef __AARCH64EB__
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#define ELF_DATA ELFDATA2MSB
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#else
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#define ELF_DATA ELFDATA2LSB
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#endif
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#define ELF_ARCH EM_AARCH64
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/*
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* This yields a string that ld.so will use to load implementation
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* specific libraries for optimization. This is more specific in
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* intent than poking at uname or /proc/cpuinfo.
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*/
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#define ELF_PLATFORM_SIZE 16
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#ifdef __AARCH64EB__
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#define ELF_PLATFORM ("aarch64_be")
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#else
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#define ELF_PLATFORM ("aarch64")
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#endif
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/*
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* This is used to ensure we don't load something for the wrong architecture.
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*/
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#define elf_check_arch(x) ((x)->e_machine == EM_AARCH64)
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#define elf_read_implies_exec(ex,stk) (stk != EXSTACK_DISABLE_X)
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#define CORE_DUMP_USE_REGSET
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#define ELF_EXEC_PAGESIZE PAGE_SIZE
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/*
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* This is the base location for PIE (ET_DYN with INTERP) loads. On
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* 64-bit, this is above 4GB to leave the entire 32-bit address
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* space open for things that want to use the area for 32-bit pointers.
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*/
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#define ELF_ET_DYN_BASE (2 * TASK_SIZE_64 / 3)
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#ifndef __ASSEMBLY__
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typedef unsigned long elf_greg_t;
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#define ELF_NGREG (sizeof(struct user_pt_regs) / sizeof(elf_greg_t))
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#define ELF_CORE_COPY_REGS(dest, regs) \
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*(struct user_pt_regs *)&(dest) = (regs)->user_regs;
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typedef elf_greg_t elf_gregset_t[ELF_NGREG];
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typedef struct user_fpsimd_state elf_fpregset_t;
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/*
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* When the program starts, a1 contains a pointer to a function to be
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* registered with atexit, as per the SVR4 ABI. A value of 0 means we have no
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* such handler.
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*/
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#define ELF_PLAT_INIT(_r, load_addr) (_r)->regs[0] = 0
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#define SET_PERSONALITY(ex) \
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({ \
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clear_thread_flag(TIF_32BIT); \
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current->personality &= ~READ_IMPLIES_EXEC; \
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})
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/* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes */
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#define ARCH_DLINFO \
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do { \
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NEW_AUX_ENT(AT_SYSINFO_EHDR, \
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(elf_addr_t)current->mm->context.vdso); \
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} while (0)
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#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
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struct linux_binprm;
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extern int arch_setup_additional_pages(struct linux_binprm *bprm,
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int uses_interp);
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/* 1GB of VA */
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#ifdef CONFIG_COMPAT
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#define STACK_RND_MASK (test_thread_flag(TIF_32BIT) ? \
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0x7ff >> (PAGE_SHIFT - 12) : \
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0x3ffff >> (PAGE_SHIFT - 12))
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#else
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#define STACK_RND_MASK (0x3ffff >> (PAGE_SHIFT - 12))
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#endif
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#ifdef __AARCH64EB__
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#define COMPAT_ELF_PLATFORM ("v8b")
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#else
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#define COMPAT_ELF_PLATFORM ("v8l")
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#endif
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#ifdef CONFIG_COMPAT
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/* PIE load location for compat arm. Must match ARM ELF_ET_DYN_BASE. */
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#define COMPAT_ELF_ET_DYN_BASE 0x000400000UL
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/* AArch32 registers. */
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#define COMPAT_ELF_NGREG 18
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typedef unsigned int compat_elf_greg_t;
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typedef compat_elf_greg_t compat_elf_gregset_t[COMPAT_ELF_NGREG];
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/* AArch32 EABI. */
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#define EF_ARM_EABI_MASK 0xff000000
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#define compat_elf_check_arch(x) (system_supports_32bit_el0() && \
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((x)->e_machine == EM_ARM) && \
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((x)->e_flags & EF_ARM_EABI_MASK))
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#define compat_start_thread compat_start_thread
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/*
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* Unlike the native SET_PERSONALITY macro, the compat version inherits
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* READ_IMPLIES_EXEC across a fork() since this is the behaviour on
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* arch/arm/.
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*/
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#define COMPAT_SET_PERSONALITY(ex) \
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({ \
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set_thread_flag(TIF_32BIT); \
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})
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#define COMPAT_ARCH_DLINFO
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extern int aarch32_setup_vectors_page(struct linux_binprm *bprm,
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int uses_interp);
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#define compat_arch_setup_additional_pages \
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aarch32_setup_vectors_page
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#endif /* CONFIG_COMPAT */
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#endif /* !__ASSEMBLY__ */
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#endif
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