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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 655 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
647 lines
16 KiB
C
647 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* adv7183.c Analog Devices ADV7183 video decoder driver
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*
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* Copyright (c) 2011 Analog Devices Inc.
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*/
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/gpio.h>
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#include <linux/i2c.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include <linux/videodev2.h>
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#include <media/i2c/adv7183.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-device.h>
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#include "adv7183_regs.h"
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struct adv7183 {
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struct v4l2_subdev sd;
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struct v4l2_ctrl_handler hdl;
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v4l2_std_id std; /* Current set standard */
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u32 input;
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u32 output;
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unsigned reset_pin;
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unsigned oe_pin;
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struct v4l2_mbus_framefmt fmt;
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};
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/* EXAMPLES USING 27 MHz CLOCK
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* Mode 1 CVBS Input (Composite Video on AIN5)
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* All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P15 to P8.
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*/
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static const unsigned char adv7183_init_regs[] = {
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ADV7183_IN_CTRL, 0x04, /* CVBS input on AIN5 */
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ADV7183_DIGI_CLAMP_CTRL_1, 0x00, /* Slow down digital clamps */
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ADV7183_SHAP_FILT_CTRL, 0x41, /* Set CSFM to SH1 */
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ADV7183_ADC_CTRL, 0x16, /* Power down ADC 1 and ADC 2 */
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ADV7183_CTI_DNR_CTRL_4, 0x04, /* Set DNR threshold to 4 for flat response */
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/* ADI recommended programming sequence */
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ADV7183_ADI_CTRL, 0x80,
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ADV7183_CTI_DNR_CTRL_4, 0x20,
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0x52, 0x18,
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0x58, 0xED,
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0x77, 0xC5,
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0x7C, 0x93,
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0x7D, 0x00,
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0xD0, 0x48,
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0xD5, 0xA0,
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0xD7, 0xEA,
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ADV7183_SD_SATURATION_CR, 0x3E,
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ADV7183_PAL_V_END, 0x3E,
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ADV7183_PAL_F_TOGGLE, 0x0F,
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ADV7183_ADI_CTRL, 0x00,
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};
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static inline struct adv7183 *to_adv7183(struct v4l2_subdev *sd)
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{
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return container_of(sd, struct adv7183, sd);
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}
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static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
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{
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return &container_of(ctrl->handler, struct adv7183, hdl)->sd;
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}
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static inline int adv7183_read(struct v4l2_subdev *sd, unsigned char reg)
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{
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struct i2c_client *client = v4l2_get_subdevdata(sd);
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return i2c_smbus_read_byte_data(client, reg);
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}
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static inline int adv7183_write(struct v4l2_subdev *sd, unsigned char reg,
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unsigned char value)
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{
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struct i2c_client *client = v4l2_get_subdevdata(sd);
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return i2c_smbus_write_byte_data(client, reg, value);
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}
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static int adv7183_writeregs(struct v4l2_subdev *sd,
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const unsigned char *regs, unsigned int num)
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{
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unsigned char reg, data;
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unsigned int cnt = 0;
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if (num & 0x1) {
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v4l2_err(sd, "invalid regs array\n");
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return -1;
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}
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while (cnt < num) {
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reg = *regs++;
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data = *regs++;
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cnt += 2;
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adv7183_write(sd, reg, data);
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}
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return 0;
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}
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static int adv7183_log_status(struct v4l2_subdev *sd)
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{
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struct adv7183 *decoder = to_adv7183(sd);
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v4l2_info(sd, "adv7183: Input control = 0x%02x\n",
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adv7183_read(sd, ADV7183_IN_CTRL));
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v4l2_info(sd, "adv7183: Video selection = 0x%02x\n",
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adv7183_read(sd, ADV7183_VD_SEL));
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v4l2_info(sd, "adv7183: Output control = 0x%02x\n",
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adv7183_read(sd, ADV7183_OUT_CTRL));
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v4l2_info(sd, "adv7183: Extended output control = 0x%02x\n",
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adv7183_read(sd, ADV7183_EXT_OUT_CTRL));
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v4l2_info(sd, "adv7183: Autodetect enable = 0x%02x\n",
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adv7183_read(sd, ADV7183_AUTO_DET_EN));
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v4l2_info(sd, "adv7183: Contrast = 0x%02x\n",
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adv7183_read(sd, ADV7183_CONTRAST));
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v4l2_info(sd, "adv7183: Brightness = 0x%02x\n",
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adv7183_read(sd, ADV7183_BRIGHTNESS));
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v4l2_info(sd, "adv7183: Hue = 0x%02x\n",
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adv7183_read(sd, ADV7183_HUE));
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v4l2_info(sd, "adv7183: Default value Y = 0x%02x\n",
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adv7183_read(sd, ADV7183_DEF_Y));
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v4l2_info(sd, "adv7183: Default value C = 0x%02x\n",
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adv7183_read(sd, ADV7183_DEF_C));
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v4l2_info(sd, "adv7183: ADI control = 0x%02x\n",
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adv7183_read(sd, ADV7183_ADI_CTRL));
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v4l2_info(sd, "adv7183: Power Management = 0x%02x\n",
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adv7183_read(sd, ADV7183_POW_MANAGE));
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v4l2_info(sd, "adv7183: Status 1 2 and 3 = 0x%02x 0x%02x 0x%02x\n",
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adv7183_read(sd, ADV7183_STATUS_1),
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adv7183_read(sd, ADV7183_STATUS_2),
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adv7183_read(sd, ADV7183_STATUS_3));
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v4l2_info(sd, "adv7183: Ident = 0x%02x\n",
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adv7183_read(sd, ADV7183_IDENT));
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v4l2_info(sd, "adv7183: Analog clamp control = 0x%02x\n",
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adv7183_read(sd, ADV7183_ANAL_CLAMP_CTRL));
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v4l2_info(sd, "adv7183: Digital clamp control 1 = 0x%02x\n",
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adv7183_read(sd, ADV7183_DIGI_CLAMP_CTRL_1));
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v4l2_info(sd, "adv7183: Shaping filter control 1 and 2 = 0x%02x 0x%02x\n",
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adv7183_read(sd, ADV7183_SHAP_FILT_CTRL),
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adv7183_read(sd, ADV7183_SHAP_FILT_CTRL_2));
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v4l2_info(sd, "adv7183: Comb filter control = 0x%02x\n",
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adv7183_read(sd, ADV7183_COMB_FILT_CTRL));
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v4l2_info(sd, "adv7183: ADI control 2 = 0x%02x\n",
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adv7183_read(sd, ADV7183_ADI_CTRL_2));
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v4l2_info(sd, "adv7183: Pixel delay control = 0x%02x\n",
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adv7183_read(sd, ADV7183_PIX_DELAY_CTRL));
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v4l2_info(sd, "adv7183: Misc gain control = 0x%02x\n",
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adv7183_read(sd, ADV7183_MISC_GAIN_CTRL));
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v4l2_info(sd, "adv7183: AGC mode control = 0x%02x\n",
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adv7183_read(sd, ADV7183_AGC_MODE_CTRL));
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v4l2_info(sd, "adv7183: Chroma gain control 1 and 2 = 0x%02x 0x%02x\n",
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adv7183_read(sd, ADV7183_CHRO_GAIN_CTRL_1),
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adv7183_read(sd, ADV7183_CHRO_GAIN_CTRL_2));
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v4l2_info(sd, "adv7183: Luma gain control 1 and 2 = 0x%02x 0x%02x\n",
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adv7183_read(sd, ADV7183_LUMA_GAIN_CTRL_1),
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adv7183_read(sd, ADV7183_LUMA_GAIN_CTRL_2));
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v4l2_info(sd, "adv7183: Vsync field control 1 2 and 3 = 0x%02x 0x%02x 0x%02x\n",
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adv7183_read(sd, ADV7183_VS_FIELD_CTRL_1),
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adv7183_read(sd, ADV7183_VS_FIELD_CTRL_2),
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adv7183_read(sd, ADV7183_VS_FIELD_CTRL_3));
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v4l2_info(sd, "adv7183: Hsync position control 1 2 and 3 = 0x%02x 0x%02x 0x%02x\n",
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adv7183_read(sd, ADV7183_HS_POS_CTRL_1),
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adv7183_read(sd, ADV7183_HS_POS_CTRL_2),
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adv7183_read(sd, ADV7183_HS_POS_CTRL_3));
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v4l2_info(sd, "adv7183: Polarity = 0x%02x\n",
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adv7183_read(sd, ADV7183_POLARITY));
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v4l2_info(sd, "adv7183: ADC control = 0x%02x\n",
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adv7183_read(sd, ADV7183_ADC_CTRL));
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v4l2_info(sd, "adv7183: SD offset Cb and Cr = 0x%02x 0x%02x\n",
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adv7183_read(sd, ADV7183_SD_OFFSET_CB),
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adv7183_read(sd, ADV7183_SD_OFFSET_CR));
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v4l2_info(sd, "adv7183: SD saturation Cb and Cr = 0x%02x 0x%02x\n",
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adv7183_read(sd, ADV7183_SD_SATURATION_CB),
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adv7183_read(sd, ADV7183_SD_SATURATION_CR));
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v4l2_info(sd, "adv7183: Drive strength = 0x%02x\n",
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adv7183_read(sd, ADV7183_DRIVE_STR));
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v4l2_ctrl_handler_log_status(&decoder->hdl, sd->name);
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return 0;
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}
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static int adv7183_g_std(struct v4l2_subdev *sd, v4l2_std_id *std)
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{
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struct adv7183 *decoder = to_adv7183(sd);
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*std = decoder->std;
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return 0;
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}
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static int adv7183_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
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{
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struct adv7183 *decoder = to_adv7183(sd);
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int reg;
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reg = adv7183_read(sd, ADV7183_IN_CTRL) & 0xF;
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if (std == V4L2_STD_PAL_60)
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reg |= 0x60;
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else if (std == V4L2_STD_NTSC_443)
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reg |= 0x70;
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else if (std == V4L2_STD_PAL_N)
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reg |= 0x90;
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else if (std == V4L2_STD_PAL_M)
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reg |= 0xA0;
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else if (std == V4L2_STD_PAL_Nc)
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reg |= 0xC0;
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else if (std & V4L2_STD_PAL)
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reg |= 0x80;
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else if (std & V4L2_STD_NTSC)
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reg |= 0x50;
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else if (std & V4L2_STD_SECAM)
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reg |= 0xE0;
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else
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return -EINVAL;
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adv7183_write(sd, ADV7183_IN_CTRL, reg);
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decoder->std = std;
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return 0;
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}
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static int adv7183_reset(struct v4l2_subdev *sd, u32 val)
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{
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int reg;
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reg = adv7183_read(sd, ADV7183_POW_MANAGE) | 0x80;
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adv7183_write(sd, ADV7183_POW_MANAGE, reg);
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/* wait 5ms before any further i2c writes are performed */
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usleep_range(5000, 10000);
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return 0;
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}
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static int adv7183_s_routing(struct v4l2_subdev *sd,
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u32 input, u32 output, u32 config)
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{
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struct adv7183 *decoder = to_adv7183(sd);
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int reg;
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if ((input > ADV7183_COMPONENT1) || (output > ADV7183_16BIT_OUT))
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return -EINVAL;
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if (input != decoder->input) {
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decoder->input = input;
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reg = adv7183_read(sd, ADV7183_IN_CTRL) & 0xF0;
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switch (input) {
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case ADV7183_COMPOSITE1:
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reg |= 0x1;
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break;
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case ADV7183_COMPOSITE2:
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reg |= 0x2;
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break;
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case ADV7183_COMPOSITE3:
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reg |= 0x3;
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break;
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case ADV7183_COMPOSITE4:
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reg |= 0x4;
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break;
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case ADV7183_COMPOSITE5:
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reg |= 0x5;
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break;
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case ADV7183_COMPOSITE6:
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reg |= 0xB;
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break;
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case ADV7183_COMPOSITE7:
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reg |= 0xC;
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break;
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case ADV7183_COMPOSITE8:
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reg |= 0xD;
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break;
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case ADV7183_COMPOSITE9:
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reg |= 0xE;
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break;
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case ADV7183_COMPOSITE10:
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reg |= 0xF;
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break;
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case ADV7183_SVIDEO0:
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reg |= 0x6;
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break;
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case ADV7183_SVIDEO1:
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reg |= 0x7;
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break;
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case ADV7183_SVIDEO2:
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reg |= 0x8;
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break;
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case ADV7183_COMPONENT0:
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reg |= 0x9;
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break;
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case ADV7183_COMPONENT1:
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reg |= 0xA;
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break;
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default:
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break;
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}
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adv7183_write(sd, ADV7183_IN_CTRL, reg);
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}
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if (output != decoder->output) {
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decoder->output = output;
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reg = adv7183_read(sd, ADV7183_OUT_CTRL) & 0xC0;
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switch (output) {
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case ADV7183_16BIT_OUT:
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reg |= 0x9;
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break;
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default:
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reg |= 0xC;
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break;
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}
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adv7183_write(sd, ADV7183_OUT_CTRL, reg);
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}
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return 0;
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}
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static int adv7183_s_ctrl(struct v4l2_ctrl *ctrl)
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{
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struct v4l2_subdev *sd = to_sd(ctrl);
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int val = ctrl->val;
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switch (ctrl->id) {
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case V4L2_CID_BRIGHTNESS:
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if (val < 0)
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val = 127 - val;
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adv7183_write(sd, ADV7183_BRIGHTNESS, val);
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break;
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case V4L2_CID_CONTRAST:
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adv7183_write(sd, ADV7183_CONTRAST, val);
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break;
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case V4L2_CID_SATURATION:
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adv7183_write(sd, ADV7183_SD_SATURATION_CB, val >> 8);
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adv7183_write(sd, ADV7183_SD_SATURATION_CR, (val & 0xFF));
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break;
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case V4L2_CID_HUE:
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adv7183_write(sd, ADV7183_SD_OFFSET_CB, val >> 8);
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adv7183_write(sd, ADV7183_SD_OFFSET_CR, (val & 0xFF));
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int adv7183_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
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{
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struct adv7183 *decoder = to_adv7183(sd);
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int reg;
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/* enable autodetection block */
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reg = adv7183_read(sd, ADV7183_IN_CTRL) & 0xF;
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adv7183_write(sd, ADV7183_IN_CTRL, reg);
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/* wait autodetection switch */
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mdelay(10);
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/* get autodetection result */
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reg = adv7183_read(sd, ADV7183_STATUS_1);
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switch ((reg >> 0x4) & 0x7) {
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case 0:
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*std &= V4L2_STD_NTSC;
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break;
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case 1:
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*std &= V4L2_STD_NTSC_443;
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break;
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case 2:
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*std &= V4L2_STD_PAL_M;
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break;
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case 3:
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*std &= V4L2_STD_PAL_60;
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break;
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case 4:
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*std &= V4L2_STD_PAL;
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break;
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case 5:
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*std &= V4L2_STD_SECAM;
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break;
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case 6:
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*std &= V4L2_STD_PAL_Nc;
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break;
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case 7:
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*std &= V4L2_STD_SECAM;
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break;
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default:
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*std = V4L2_STD_UNKNOWN;
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break;
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}
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/* after std detection, write back user set std */
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adv7183_s_std(sd, decoder->std);
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return 0;
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}
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static int adv7183_g_input_status(struct v4l2_subdev *sd, u32 *status)
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{
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int reg;
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*status = V4L2_IN_ST_NO_SIGNAL;
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reg = adv7183_read(sd, ADV7183_STATUS_1);
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if (reg < 0)
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return reg;
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if (reg & 0x1)
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*status = 0;
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return 0;
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}
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static int adv7183_enum_mbus_code(struct v4l2_subdev *sd,
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struct v4l2_subdev_pad_config *cfg,
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struct v4l2_subdev_mbus_code_enum *code)
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{
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if (code->pad || code->index > 0)
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return -EINVAL;
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code->code = MEDIA_BUS_FMT_UYVY8_2X8;
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return 0;
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}
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static int adv7183_set_fmt(struct v4l2_subdev *sd,
|
|
struct v4l2_subdev_pad_config *cfg,
|
|
struct v4l2_subdev_format *format)
|
|
{
|
|
struct adv7183 *decoder = to_adv7183(sd);
|
|
struct v4l2_mbus_framefmt *fmt = &format->format;
|
|
|
|
if (format->pad)
|
|
return -EINVAL;
|
|
|
|
fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
|
|
fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
|
|
if (decoder->std & V4L2_STD_525_60) {
|
|
fmt->field = V4L2_FIELD_SEQ_TB;
|
|
fmt->width = 720;
|
|
fmt->height = 480;
|
|
} else {
|
|
fmt->field = V4L2_FIELD_SEQ_BT;
|
|
fmt->width = 720;
|
|
fmt->height = 576;
|
|
}
|
|
if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
|
|
decoder->fmt = *fmt;
|
|
else
|
|
cfg->try_fmt = *fmt;
|
|
return 0;
|
|
}
|
|
|
|
static int adv7183_get_fmt(struct v4l2_subdev *sd,
|
|
struct v4l2_subdev_pad_config *cfg,
|
|
struct v4l2_subdev_format *format)
|
|
{
|
|
struct adv7183 *decoder = to_adv7183(sd);
|
|
|
|
if (format->pad)
|
|
return -EINVAL;
|
|
|
|
format->format = decoder->fmt;
|
|
return 0;
|
|
}
|
|
|
|
static int adv7183_s_stream(struct v4l2_subdev *sd, int enable)
|
|
{
|
|
struct adv7183 *decoder = to_adv7183(sd);
|
|
|
|
if (enable)
|
|
gpio_set_value(decoder->oe_pin, 0);
|
|
else
|
|
gpio_set_value(decoder->oe_pin, 1);
|
|
udelay(1);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_VIDEO_ADV_DEBUG
|
|
static int adv7183_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
|
|
{
|
|
reg->val = adv7183_read(sd, reg->reg & 0xff);
|
|
reg->size = 1;
|
|
return 0;
|
|
}
|
|
|
|
static int adv7183_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
|
|
{
|
|
adv7183_write(sd, reg->reg & 0xff, reg->val & 0xff);
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static const struct v4l2_ctrl_ops adv7183_ctrl_ops = {
|
|
.s_ctrl = adv7183_s_ctrl,
|
|
};
|
|
|
|
static const struct v4l2_subdev_core_ops adv7183_core_ops = {
|
|
.log_status = adv7183_log_status,
|
|
.reset = adv7183_reset,
|
|
#ifdef CONFIG_VIDEO_ADV_DEBUG
|
|
.g_register = adv7183_g_register,
|
|
.s_register = adv7183_s_register,
|
|
#endif
|
|
};
|
|
|
|
static const struct v4l2_subdev_video_ops adv7183_video_ops = {
|
|
.g_std = adv7183_g_std,
|
|
.s_std = adv7183_s_std,
|
|
.s_routing = adv7183_s_routing,
|
|
.querystd = adv7183_querystd,
|
|
.g_input_status = adv7183_g_input_status,
|
|
.s_stream = adv7183_s_stream,
|
|
};
|
|
|
|
static const struct v4l2_subdev_pad_ops adv7183_pad_ops = {
|
|
.enum_mbus_code = adv7183_enum_mbus_code,
|
|
.get_fmt = adv7183_get_fmt,
|
|
.set_fmt = adv7183_set_fmt,
|
|
};
|
|
|
|
static const struct v4l2_subdev_ops adv7183_ops = {
|
|
.core = &adv7183_core_ops,
|
|
.video = &adv7183_video_ops,
|
|
.pad = &adv7183_pad_ops,
|
|
};
|
|
|
|
static int adv7183_probe(struct i2c_client *client,
|
|
const struct i2c_device_id *id)
|
|
{
|
|
struct adv7183 *decoder;
|
|
struct v4l2_subdev *sd;
|
|
struct v4l2_ctrl_handler *hdl;
|
|
int ret;
|
|
struct v4l2_subdev_format fmt = {
|
|
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
|
|
};
|
|
const unsigned *pin_array;
|
|
|
|
/* Check if the adapter supports the needed features */
|
|
if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
|
|
return -EIO;
|
|
|
|
v4l_info(client, "chip found @ 0x%02x (%s)\n",
|
|
client->addr << 1, client->adapter->name);
|
|
|
|
pin_array = client->dev.platform_data;
|
|
if (pin_array == NULL)
|
|
return -EINVAL;
|
|
|
|
decoder = devm_kzalloc(&client->dev, sizeof(*decoder), GFP_KERNEL);
|
|
if (decoder == NULL)
|
|
return -ENOMEM;
|
|
|
|
decoder->reset_pin = pin_array[0];
|
|
decoder->oe_pin = pin_array[1];
|
|
|
|
if (devm_gpio_request_one(&client->dev, decoder->reset_pin,
|
|
GPIOF_OUT_INIT_LOW, "ADV7183 Reset")) {
|
|
v4l_err(client, "failed to request GPIO %d\n", decoder->reset_pin);
|
|
return -EBUSY;
|
|
}
|
|
|
|
if (devm_gpio_request_one(&client->dev, decoder->oe_pin,
|
|
GPIOF_OUT_INIT_HIGH,
|
|
"ADV7183 Output Enable")) {
|
|
v4l_err(client, "failed to request GPIO %d\n", decoder->oe_pin);
|
|
return -EBUSY;
|
|
}
|
|
|
|
sd = &decoder->sd;
|
|
v4l2_i2c_subdev_init(sd, client, &adv7183_ops);
|
|
|
|
hdl = &decoder->hdl;
|
|
v4l2_ctrl_handler_init(hdl, 4);
|
|
v4l2_ctrl_new_std(hdl, &adv7183_ctrl_ops,
|
|
V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
|
|
v4l2_ctrl_new_std(hdl, &adv7183_ctrl_ops,
|
|
V4L2_CID_CONTRAST, 0, 0xFF, 1, 0x80);
|
|
v4l2_ctrl_new_std(hdl, &adv7183_ctrl_ops,
|
|
V4L2_CID_SATURATION, 0, 0xFFFF, 1, 0x8080);
|
|
v4l2_ctrl_new_std(hdl, &adv7183_ctrl_ops,
|
|
V4L2_CID_HUE, 0, 0xFFFF, 1, 0x8080);
|
|
/* hook the control handler into the driver */
|
|
sd->ctrl_handler = hdl;
|
|
if (hdl->error) {
|
|
ret = hdl->error;
|
|
|
|
v4l2_ctrl_handler_free(hdl);
|
|
return ret;
|
|
}
|
|
|
|
/* v4l2 doesn't support an autodetect standard, pick PAL as default */
|
|
decoder->std = V4L2_STD_PAL;
|
|
decoder->input = ADV7183_COMPOSITE4;
|
|
decoder->output = ADV7183_8BIT_OUT;
|
|
|
|
/* reset chip */
|
|
/* reset pulse width at least 5ms */
|
|
mdelay(10);
|
|
gpio_set_value(decoder->reset_pin, 1);
|
|
/* wait 5ms before any further i2c writes are performed */
|
|
mdelay(5);
|
|
|
|
adv7183_writeregs(sd, adv7183_init_regs, ARRAY_SIZE(adv7183_init_regs));
|
|
adv7183_s_std(sd, decoder->std);
|
|
fmt.format.width = 720;
|
|
fmt.format.height = 576;
|
|
adv7183_set_fmt(sd, NULL, &fmt);
|
|
|
|
/* initialize the hardware to the default control values */
|
|
ret = v4l2_ctrl_handler_setup(hdl);
|
|
if (ret) {
|
|
v4l2_ctrl_handler_free(hdl);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int adv7183_remove(struct i2c_client *client)
|
|
{
|
|
struct v4l2_subdev *sd = i2c_get_clientdata(client);
|
|
|
|
v4l2_device_unregister_subdev(sd);
|
|
v4l2_ctrl_handler_free(sd->ctrl_handler);
|
|
return 0;
|
|
}
|
|
|
|
static const struct i2c_device_id adv7183_id[] = {
|
|
{"adv7183", 0},
|
|
{},
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(i2c, adv7183_id);
|
|
|
|
static struct i2c_driver adv7183_driver = {
|
|
.driver = {
|
|
.name = "adv7183",
|
|
},
|
|
.probe = adv7183_probe,
|
|
.remove = adv7183_remove,
|
|
.id_table = adv7183_id,
|
|
};
|
|
|
|
module_i2c_driver(adv7183_driver);
|
|
|
|
MODULE_DESCRIPTION("Analog Devices ADV7183 video decoder driver");
|
|
MODULE_AUTHOR("Scott Jiang <Scott.Jiang.Linux@gmail.com>");
|
|
MODULE_LICENSE("GPL v2");
|