mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 10:46:40 +07:00
e0d8b13ae1
Where devices only have one consumer, passing a consumer clock ID has no real benefit. Remove it. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
531 lines
14 KiB
C
531 lines
14 KiB
C
/*
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* OHCI HCD (Host Controller Driver) for USB.
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*
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* (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
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* (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
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* (C) Copyright 2002 Hewlett-Packard Company
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*
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* Bus Glue for pxa27x
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*
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* Written by Christopher Hoover <ch@hpl.hp.com>
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* Based on fragments of previous driver by Russell King et al.
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*
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* Modified for LH7A404 from ohci-sa1111.c
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* by Durgesh Pattamatta <pattamattad@sharpsec.com>
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*
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* Modified for pxa27x from ohci-lh7a404.c
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* by Nick Bane <nick@cecomputing.co.uk> 26-8-2004
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*
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* This file is licenced under the GPL.
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*/
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#include <linux/device.h>
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#include <linux/signal.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <mach/ohci.h>
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/*
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* UHC: USB Host Controller (OHCI-like) register definitions
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*/
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#define UHCREV (0x0000) /* UHC HCI Spec Revision */
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#define UHCHCON (0x0004) /* UHC Host Control Register */
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#define UHCCOMS (0x0008) /* UHC Command Status Register */
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#define UHCINTS (0x000C) /* UHC Interrupt Status Register */
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#define UHCINTE (0x0010) /* UHC Interrupt Enable */
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#define UHCINTD (0x0014) /* UHC Interrupt Disable */
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#define UHCHCCA (0x0018) /* UHC Host Controller Comm. Area */
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#define UHCPCED (0x001C) /* UHC Period Current Endpt Descr */
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#define UHCCHED (0x0020) /* UHC Control Head Endpt Descr */
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#define UHCCCED (0x0024) /* UHC Control Current Endpt Descr */
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#define UHCBHED (0x0028) /* UHC Bulk Head Endpt Descr */
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#define UHCBCED (0x002C) /* UHC Bulk Current Endpt Descr */
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#define UHCDHEAD (0x0030) /* UHC Done Head */
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#define UHCFMI (0x0034) /* UHC Frame Interval */
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#define UHCFMR (0x0038) /* UHC Frame Remaining */
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#define UHCFMN (0x003C) /* UHC Frame Number */
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#define UHCPERS (0x0040) /* UHC Periodic Start */
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#define UHCLS (0x0044) /* UHC Low Speed Threshold */
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#define UHCRHDA (0x0048) /* UHC Root Hub Descriptor A */
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#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
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#define UHCRHDA_OCPM (1 << 11) /* Over Current Protection Mode */
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#define UHCRHDA_POTPGT(x) \
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(((x) & 0xff) << 24) /* Power On To Power Good Time */
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#define UHCRHDB (0x004C) /* UHC Root Hub Descriptor B */
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#define UHCRHS (0x0050) /* UHC Root Hub Status */
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#define UHCRHPS1 (0x0054) /* UHC Root Hub Port 1 Status */
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#define UHCRHPS2 (0x0058) /* UHC Root Hub Port 2 Status */
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#define UHCRHPS3 (0x005C) /* UHC Root Hub Port 3 Status */
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#define UHCSTAT (0x0060) /* UHC Status Register */
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#define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
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#define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
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#define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
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#define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
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#define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
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#define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
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#define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
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#define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
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#define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
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#define UHCHR (0x0064) /* UHC Reset Register */
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#define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
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#define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
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#define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
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#define UHCHR_PCPL (1 << 7) /* Power control polarity low */
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#define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
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#define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
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#define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
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#define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
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#define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
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#define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
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#define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
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#define UHCHIE (0x0068) /* UHC Interrupt Enable Register*/
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#define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
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#define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
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#define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
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#define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
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#define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
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Interrupt Enable*/
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#define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
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#define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
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#define UHCHIT (0x006C) /* UHC Interrupt Test register */
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#define PXA_UHC_MAX_PORTNUM 3
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struct pxa27x_ohci {
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/* must be 1st member here for hcd_to_ohci() to work */
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struct ohci_hcd ohci;
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struct device *dev;
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struct clk *clk;
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void __iomem *mmio_base;
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};
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#define to_pxa27x_ohci(hcd) (struct pxa27x_ohci *)hcd_to_ohci(hcd)
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/*
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PMM_NPS_MODE -- PMM Non-power switching mode
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Ports are powered continuously.
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PMM_GLOBAL_MODE -- PMM global switching mode
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All ports are powered at the same time.
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PMM_PERPORT_MODE -- PMM per port switching mode
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Ports are powered individually.
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*/
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static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *ohci, int mode)
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{
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uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA);
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uint32_t uhcrhdb = __raw_readl(ohci->mmio_base + UHCRHDB);
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switch (mode) {
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case PMM_NPS_MODE:
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uhcrhda |= RH_A_NPS;
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break;
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case PMM_GLOBAL_MODE:
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uhcrhda &= ~(RH_A_NPS & RH_A_PSM);
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break;
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case PMM_PERPORT_MODE:
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uhcrhda &= ~(RH_A_NPS);
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uhcrhda |= RH_A_PSM;
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/* Set port power control mask bits, only 3 ports. */
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uhcrhdb |= (0x7<<17);
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break;
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default:
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printk( KERN_ERR
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"Invalid mode %d, set to non-power switch mode.\n",
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mode );
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uhcrhda |= RH_A_NPS;
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}
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__raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA);
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__raw_writel(uhcrhdb, ohci->mmio_base + UHCRHDB);
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return 0;
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}
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extern int usb_disabled(void);
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/*-------------------------------------------------------------------------*/
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static inline void pxa27x_setup_hc(struct pxa27x_ohci *ohci,
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struct pxaohci_platform_data *inf)
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{
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uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR);
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uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA);
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if (inf->flags & ENABLE_PORT1)
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uhchr &= ~UHCHR_SSEP1;
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if (inf->flags & ENABLE_PORT2)
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uhchr &= ~UHCHR_SSEP2;
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if (inf->flags & ENABLE_PORT3)
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uhchr &= ~UHCHR_SSEP3;
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if (inf->flags & POWER_CONTROL_LOW)
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uhchr |= UHCHR_PCPL;
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if (inf->flags & POWER_SENSE_LOW)
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uhchr |= UHCHR_PSPL;
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if (inf->flags & NO_OC_PROTECTION)
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uhcrhda |= UHCRHDA_NOCP;
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if (inf->flags & OC_MODE_PERPORT)
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uhcrhda |= UHCRHDA_OCPM;
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if (inf->power_on_delay) {
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uhcrhda &= ~UHCRHDA_POTPGT(0xff);
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uhcrhda |= UHCRHDA_POTPGT(inf->power_on_delay / 2);
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}
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__raw_writel(uhchr, ohci->mmio_base + UHCHR);
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__raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA);
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}
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static inline void pxa27x_reset_hc(struct pxa27x_ohci *ohci)
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{
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uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR);
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__raw_writel(uhchr | UHCHR_FHR, ohci->mmio_base + UHCHR);
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udelay(11);
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__raw_writel(uhchr & ~UHCHR_FHR, ohci->mmio_base + UHCHR);
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}
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#ifdef CONFIG_CPU_PXA27x
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extern void pxa27x_clear_otgph(void);
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#else
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#define pxa27x_clear_otgph() do {} while (0)
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#endif
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static int pxa27x_start_hc(struct pxa27x_ohci *ohci, struct device *dev)
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{
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int retval = 0;
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struct pxaohci_platform_data *inf;
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uint32_t uhchr;
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inf = dev->platform_data;
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clk_enable(ohci->clk);
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pxa27x_reset_hc(ohci);
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uhchr = __raw_readl(ohci->mmio_base + UHCHR) | UHCHR_FSBIR;
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__raw_writel(uhchr, ohci->mmio_base + UHCHR);
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while (__raw_readl(ohci->mmio_base + UHCHR) & UHCHR_FSBIR)
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cpu_relax();
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pxa27x_setup_hc(ohci, inf);
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if (inf->init)
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retval = inf->init(dev);
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if (retval < 0)
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return retval;
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uhchr = __raw_readl(ohci->mmio_base + UHCHR) & ~UHCHR_SSE;
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__raw_writel(uhchr, ohci->mmio_base + UHCHR);
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__raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, ohci->mmio_base + UHCHIE);
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/* Clear any OTG Pin Hold */
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pxa27x_clear_otgph();
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return 0;
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}
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static void pxa27x_stop_hc(struct pxa27x_ohci *ohci, struct device *dev)
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{
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struct pxaohci_platform_data *inf;
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uint32_t uhccoms;
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inf = dev->platform_data;
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if (inf->exit)
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inf->exit(dev);
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pxa27x_reset_hc(ohci);
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/* Host Controller Reset */
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uhccoms = __raw_readl(ohci->mmio_base + UHCCOMS) | 0x01;
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__raw_writel(uhccoms, ohci->mmio_base + UHCCOMS);
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udelay(10);
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clk_disable(ohci->clk);
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}
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/*-------------------------------------------------------------------------*/
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/* configure so an HC device and id are always provided */
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/* always called with process context; sleeping is OK */
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/**
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* usb_hcd_pxa27x_probe - initialize pxa27x-based HCDs
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* Context: !in_interrupt()
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*
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* Allocates basic resources for this USB host controller, and
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* then invokes the start() method for the HCD associated with it
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* through the hotplug entry's driver_data.
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*
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*/
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int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device *pdev)
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{
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int retval, irq;
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struct usb_hcd *hcd;
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struct pxaohci_platform_data *inf;
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struct pxa27x_ohci *ohci;
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struct resource *r;
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struct clk *usb_clk;
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inf = pdev->dev.platform_data;
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if (!inf)
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return -ENODEV;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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pr_err("no resource of IORESOURCE_IRQ");
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return -ENXIO;
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}
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usb_clk = clk_get(&pdev->dev, NULL);
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if (IS_ERR(usb_clk))
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return PTR_ERR(usb_clk);
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hcd = usb_create_hcd (driver, &pdev->dev, "pxa27x");
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if (!hcd)
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return -ENOMEM;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!r) {
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pr_err("no resource of IORESOURCE_MEM");
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retval = -ENXIO;
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goto err1;
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}
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hcd->rsrc_start = r->start;
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hcd->rsrc_len = resource_size(r);
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if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
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pr_debug("request_mem_region failed");
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retval = -EBUSY;
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goto err1;
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}
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hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
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if (!hcd->regs) {
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pr_debug("ioremap failed");
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retval = -ENOMEM;
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goto err2;
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}
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/* initialize "struct pxa27x_ohci" */
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ohci = (struct pxa27x_ohci *)hcd_to_ohci(hcd);
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ohci->dev = &pdev->dev;
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ohci->clk = usb_clk;
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ohci->mmio_base = (void __iomem *)hcd->regs;
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if ((retval = pxa27x_start_hc(ohci, &pdev->dev)) < 0) {
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pr_debug("pxa27x_start_hc failed");
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goto err3;
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}
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/* Select Power Management Mode */
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pxa27x_ohci_select_pmm(ohci, inf->port_mode);
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if (inf->power_budget)
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hcd->power_budget = inf->power_budget;
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ohci_hcd_init(hcd_to_ohci(hcd));
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retval = usb_add_hcd(hcd, irq, IRQF_DISABLED);
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if (retval == 0)
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return retval;
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pxa27x_stop_hc(ohci, &pdev->dev);
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err3:
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iounmap(hcd->regs);
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err2:
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release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
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err1:
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usb_put_hcd(hcd);
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clk_put(usb_clk);
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return retval;
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}
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/* may be called without controller electrically present */
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/* may be called with controller, bus, and devices active */
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/**
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* usb_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs
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* @dev: USB Host Controller being removed
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* Context: !in_interrupt()
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*
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* Reverses the effect of usb_hcd_pxa27x_probe(), first invoking
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* the HCD's stop() method. It is always called from a thread
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* context, normally "rmmod", "apmd", or something similar.
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*
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*/
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void usb_hcd_pxa27x_remove (struct usb_hcd *hcd, struct platform_device *pdev)
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{
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struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
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usb_remove_hcd(hcd);
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pxa27x_stop_hc(ohci, &pdev->dev);
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iounmap(hcd->regs);
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release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
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usb_put_hcd(hcd);
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clk_put(ohci->clk);
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}
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/*-------------------------------------------------------------------------*/
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static int __devinit
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ohci_pxa27x_start (struct usb_hcd *hcd)
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{
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struct ohci_hcd *ohci = hcd_to_ohci (hcd);
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int ret;
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ohci_dbg (ohci, "ohci_pxa27x_start, ohci:%p", ohci);
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/* The value of NDP in roothub_a is incorrect on this hardware */
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ohci->num_ports = 3;
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if ((ret = ohci_init(ohci)) < 0)
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return ret;
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if ((ret = ohci_run (ohci)) < 0) {
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err ("can't start %s", hcd->self.bus_name);
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ohci_stop (hcd);
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return ret;
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}
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return 0;
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}
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/*-------------------------------------------------------------------------*/
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static const struct hc_driver ohci_pxa27x_hc_driver = {
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.description = hcd_name,
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.product_desc = "PXA27x OHCI",
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.hcd_priv_size = sizeof(struct pxa27x_ohci),
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/*
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* generic hardware linkage
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*/
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.irq = ohci_irq,
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.flags = HCD_USB11 | HCD_MEMORY,
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/*
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* basic lifecycle operations
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*/
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.start = ohci_pxa27x_start,
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.stop = ohci_stop,
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.shutdown = ohci_shutdown,
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/*
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* managing i/o requests and associated device resources
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*/
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.urb_enqueue = ohci_urb_enqueue,
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.urb_dequeue = ohci_urb_dequeue,
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.endpoint_disable = ohci_endpoint_disable,
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/*
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* scheduling support
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*/
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.get_frame_number = ohci_get_frame,
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/*
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* root hub support
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*/
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.hub_status_data = ohci_hub_status_data,
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.hub_control = ohci_hub_control,
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#ifdef CONFIG_PM
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.bus_suspend = ohci_bus_suspend,
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.bus_resume = ohci_bus_resume,
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#endif
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.start_port_reset = ohci_start_port_reset,
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};
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/*-------------------------------------------------------------------------*/
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|
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static int ohci_hcd_pxa27x_drv_probe(struct platform_device *pdev)
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{
|
|
pr_debug ("In ohci_hcd_pxa27x_drv_probe");
|
|
|
|
if (usb_disabled())
|
|
return -ENODEV;
|
|
|
|
return usb_hcd_pxa27x_probe(&ohci_pxa27x_hc_driver, pdev);
|
|
}
|
|
|
|
static int ohci_hcd_pxa27x_drv_remove(struct platform_device *pdev)
|
|
{
|
|
struct usb_hcd *hcd = platform_get_drvdata(pdev);
|
|
|
|
usb_hcd_pxa27x_remove(hcd, pdev);
|
|
platform_set_drvdata(pdev, NULL);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int ohci_hcd_pxa27x_drv_suspend(struct platform_device *pdev, pm_message_t state)
|
|
{
|
|
struct usb_hcd *hcd = platform_get_drvdata(pdev);
|
|
struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
|
|
|
|
if (time_before(jiffies, ohci->ohci.next_statechange))
|
|
msleep(5);
|
|
ohci->ohci.next_statechange = jiffies;
|
|
|
|
pxa27x_stop_hc(ohci, &pdev->dev);
|
|
hcd->state = HC_STATE_SUSPENDED;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ohci_hcd_pxa27x_drv_resume(struct platform_device *pdev)
|
|
{
|
|
struct usb_hcd *hcd = platform_get_drvdata(pdev);
|
|
struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
|
|
int status;
|
|
|
|
if (time_before(jiffies, ohci->ohci.next_statechange))
|
|
msleep(5);
|
|
ohci->ohci.next_statechange = jiffies;
|
|
|
|
if ((status = pxa27x_start_hc(ohci, &pdev->dev)) < 0)
|
|
return status;
|
|
|
|
ohci_finish_controller_resume(hcd);
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
/* work with hotplug and coldplug */
|
|
MODULE_ALIAS("platform:pxa27x-ohci");
|
|
|
|
static struct platform_driver ohci_hcd_pxa27x_driver = {
|
|
.probe = ohci_hcd_pxa27x_drv_probe,
|
|
.remove = ohci_hcd_pxa27x_drv_remove,
|
|
.shutdown = usb_hcd_platform_shutdown,
|
|
#ifdef CONFIG_PM
|
|
.suspend = ohci_hcd_pxa27x_drv_suspend,
|
|
.resume = ohci_hcd_pxa27x_drv_resume,
|
|
#endif
|
|
.driver = {
|
|
.name = "pxa27x-ohci",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|